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From WikiChip
Information for "verilog"
Basic information
| Display title | Verilog |
| Default sort key | verilog |
| Page length (in bytes) | 3,924 |
| Page ID | 28668 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 1 |
| Counted as a content page | Yes |
| Number of subpages of this page | 2 (0 redirects; 2 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | AleksandarK (talk | contribs) |
| Date of page creation | 11:42, 25 March 2018 |
| Latest editor | AleksandarK (talk | contribs) |
| Date of latest edit | 09:23, 27 March 2018 |
| Total number of edits | 16 |
| Total number of distinct authors | 2 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
Page properties
| Transcluded templates (7) | Templates used on this page:
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Retrieved from "https://en.wikichip.org/wiki/verilog"
