Semiconductor & Computer Engineering
-
WikiChip
WikiChip
-
Architectures
Popular x86
-
Intel
- Client
- Server
- Big Cores
- Small Cores
-
AMD
Popular ARM
-
ARM
- Server
- Big
- Little
-
Cavium
-
Samsung
-
-
Chips
Popular Families
-
Ampere
-
Apple
-
Cavium
-
HiSilicon
-
MediaTek
-
NXP
-
Qualcomm
-
Renesas
-
Samsung
-
From WikiChip
Difference between revisions of "supercomputers/nersc-10"
(nersc-10) |
(→Overview) |
||
| Line 4: | Line 4: | ||
== Overview == | == Overview == | ||
NERSC-10 is a planned [[exascale]] supercomputer currently in pathfinding stages. NERSC-10 is expected to go online around the 2024 timeframe. | NERSC-10 is a planned [[exascale]] supercomputer currently in pathfinding stages. NERSC-10 is expected to go online around the 2024 timeframe. | ||
| + | |||
| + | :[[File:nersc-10 roadmap.png|600px]] | ||
== See also == | == See also == | ||
* {{sc|Aurora}} | * {{sc|Aurora}} | ||
Revision as of 05:41, 4 February 2019
NERSC-10 (no name given yet) is the successor to Perlmutter, a planned exascale supercomputer set to be operated by National Energy Research Scientific Computing Center.
Overview
NERSC-10 is a planned exascale supercomputer currently in pathfinding stages. NERSC-10 is expected to go online around the 2024 timeframe.
