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| − | {{samsung title|Exynos M4|arch}} | + | {{samsung title|Mongoose 4 (M4)|arch}} |
| | {{microarchitecture | | {{microarchitecture |
| | |atype=CPU | | |atype=CPU |
| − | |name=Cheetah | + | |name=Mongoose 4 |
| | |designer=Samsung | | |designer=Samsung |
| | |manufacturer=Samsung | | |manufacturer=Samsung |
| − | |introduction=2019 | + | |introduction=2018 |
| | |process=8 nm | | |process=8 nm |
| − | |cores=4
| + | |isa=ARMv8 |
| − | |type=Superscalar
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| − | |type 2=Superpipeline
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| − | |oooe=Yes
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| − | |speculative=Yes
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| − | |renaming=Yes
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| − | |stages=16
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| − | |decode=6-way
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| − | |isa=ARMv8.2 | |
| − | |l1i=64 KiB
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| − | |l1i per=core
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| − | |l1i desc=4-way set associative
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| − | |l1d=64 KiB
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| − | |l1d per=core
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| − | |l1d desc=8-way set associative
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| − | |l2=512 KiB
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| − | |l2 per=core
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| − | |l2 desc=8-way set associative
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| − | |l3=2 MiB
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| − | |l3 per=cluster
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| − | |l3 desc=16-way set associative
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| | |predecessor=M3 | | |predecessor=M3 |
| | |predecessor link=samsung/microarchitectures/m3 | | |predecessor link=samsung/microarchitectures/m3 |
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| | |successor link=samsung/microarchitectures/m5 | | |successor link=samsung/microarchitectures/m5 |
| | }} | | }} |
| − | '''Exynos M4''' ('''Cheetah''') is the successor to the {{\\|M3}}, an [[8 nm]] [[ARM]] microarchitecture designed by [[Samsung]] for their consumer electronics. | + | '''Mongoose 4''' ('''M4''') is the successor to the {{\\|Mongoose 3}}, an [[8 nm]] [[ARM]] microarchitecture designed by [[Samsung]] for their consumer electronics. |
| | | | |
| | == Process Technology == | | == Process Technology == |
| − | The M4 is fabricated on Samsung's [[8 nm process]] (8LPP). | + | The M4 is fabricated on Samsung's [[8 nm process]]. |
| | | | |
| | == Compiler support == | | == Compiler support == |
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| | | | |
| | == Architecture == | | == Architecture == |
| − | The M4 is an incremental microarchitecture that brought a die shrink and minor enhancements.
| + | {{empty section}} |
| − | | |
| | === Key changes from {{\\|Mongoose 3|M3}} === | | === Key changes from {{\\|Mongoose 3|M3}} === |
| − | * [[8 nm process]] (from [[10 nm]])
| + | {{empty section}} |
| − | * [[ARMv8.2]] (from [[ARMv8]])
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| − | ** Support for full FP16 scalar extension
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| − | ** Support for integer dot product extension
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| − | * Front end
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| − | ** Larger [[instruction queue]] (48 entries, up from 40)
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| − | * Back end
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| − | ** LSU execution units reorganized
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| − | ** Floating-point execution units reorganized
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| − | {{expand list}} | |
| − | | |
| − | === Block Diagram ===
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| − | ==== Individual Core ====
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| − | | |
| − | [[File:mongoose 4 block diagram.svg|900px]]
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| − | | |
| − | === Memory Hierarchy ===
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| − | * Cache
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| − | ** L1I Caches
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| − | *** 64 KiB, 4-way set associative
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| − | **** 128 B line size
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| − | **** per core
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| − | *** Parity-protected
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| − | ** L1D Cache
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| − | *** 64 KiB, 8-way set associative
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| − | **** 64 B line size
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| − | **** per core
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| − | *** 4 cycles for fastest load-to-use
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| − | *** 32 B/cycle load bandwidth
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| − | *** 16 B/cycle store bandwidth
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| − | ** L2 Cache
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| − | *** 512 KiB, 8-way set associative
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| − | *** Inclusive of L1
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| − | *** 12 cycles latency
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| − | *** 32 B/cycle bandwidth
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| − | ** L3 Cache
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| − | *** 2 MiB, 16-way set associative
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| − | **** 1 MiB slice/core
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| − | *** Exlusive of L2
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| − | *** ~37-cycle typical (NUCA)
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| − | ** BIU
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| − | *** 80 outstanding transactions
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| − | | |
| − | The M3 TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally, there is a unified L2 TLB (STLB).
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| − | | |
| − | * TLBs
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| − | ** ITLB
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| − | *** 512-entry
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| − | ** DTLB
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| − | *** 32-entry
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| − | *** 512-entry Mid-level DTLB
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| − | ** STLB
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| − | *** 4,096-entry
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| − | *** Per core
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| − | | |
| − | * BPU
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| − | ** 4K-entry main BTB
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| − | ** 128-entry µBTB
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| − | ** 64-entry return stack
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| − | ** 16K-entry L2 BTB
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| − | | |
| − | == Core ==
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| − | The core of the M4 is largely the same as {{\\|M3}}. A number of buffers have been enlarged and some of the execution units have been reorganized.
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| − | | |
| − | === Execution engine ===
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| − | ==== Floating-point cluster ====
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| − | The execution units on the M4 have been reorganized. In total, three new units were also added - a second FP square root unit, a second vector multiplication unit, and a new horizontal vector arithmetic unit.
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| − | | |
| − | :[[File:m4 fp eu pipes changes.svg|thumb|left|600px|Floating-point pipe changes.]]
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| − | | |
| − | {{clear}}
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| − | | |
| − | ==== Memory subsystem ====
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| − | [[File:m4 data cache.svg|thumb|left]]
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| − | Samsung also made an enhancement to the M4 memory subsystem. In the M3, there were three AGUs - two dedicated Load [[AGUs]] and a single dedicated Store [[AGU]]. In the M4, Samsung changed one of the dedicated Load [[AGU]]s into a generic AGU capable of handling both loads and stores. In other words, the M4 can now schedule both load and store µOPs on two ports.
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| − | | |
| − | {{clear}}
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| − | | |
| − | == All M4 Processors ==
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| − | <!-- NOTE:
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| − | This table is generated automatically from the data in the actual articles.
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| − | If a microprocessor is missing from the list, an appropriate article for it needs to be
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| − | created and tagged accordingly.
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| − | | |
| − | Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
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| − | -->
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| − | {{comp table start}}
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| − | <table class="comptable sortable tc5 tc6 tc7">
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| − | {{comp table header|main|12:List of M4-based Processors}}
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| − | {{comp table header|main|5:Main processor|2:Integrated Graphics|{{abbr|TDP}}|2:TDP down|2:TDP up}}
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| − | {{comp table header|cols|Family|Launched|Arch|Cores|%Frequency|GPU|%Frequency|P|P|Frequ.|P|Frequ.}}
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| − | {{#ask: [[Category:microprocessor models by samsung]] [[microarchitecture::M4]]
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| − | |?full page name
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| − | |?model number
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| − | |?family
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| − | |?first launched
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| − | |?microarchitecture
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| − | |?core count
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| − | |?base frequency#GHz
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| − | |?integrated gpu
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| − | |?integrated gpu base frequency
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| − | |?tdp
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| − | |?tdp down
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| − | |?tdp down frequency#GHz
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| − | |?tdp up
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| − | |?tdp up frequency#GHz
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| − | |format=template
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| − | |template=proc table 3
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| − | |userparam=14
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| − | |mainlabel=-
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| − | |valuesep=,
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| − | }}
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| − | {{comp table count|ask=[[Category:microprocessor models by samsung]] [[microarchitecture::M4]]}}
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| − | </table>
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| − | {{comp table end}}
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| − | | |
| − | == Bibliography ==
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| − | * LLVM: lib/Target/AArch64/AArch64SchedExynosM4.td
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