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Latest revision | Your text | ||
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|speculative=Yes | |speculative=Yes | ||
|renaming=Yes | |renaming=Yes | ||
− | |||
|decode=4-way | |decode=4-way | ||
|isa=ARMv8 | |isa=ARMv8 | ||
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! Compiler !! Arch-Specific || Arch-Favorable | ! Compiler !! Arch-Specific || Arch-Favorable | ||
|- | |- | ||
− | | [[GCC]] || <code>-mcpu=exynos- | + | | [[GCC]] || <code>-mcpu=exynos-m2</code> || <code>-mtune=exynos-m2</code> |
|- | |- | ||
| [[LLVM]] || <code>-mcpu=exynos-m2</code> || <code>-mtune=exynos-m2</code> | | [[LLVM]] || <code>-mcpu=exynos-m2</code> || <code>-mtune=exynos-m2</code> | ||
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*** 16 B/cycle/CPU bandwidth | *** 16 B/cycle/CPU bandwidth | ||
− | + | Mongoose 1 TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB). | |
* TLBs | * TLBs | ||
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== Core == | == Core == | ||
− | The M2 core | + | The M2 core appears to be fairly identical to the {{\\|Mongoose 1|M1}}. |
== All M2 Processors == | == All M2 Processors == |
Facts about "Exynos M2 - Microarchitectures - Samsung"
codename | Mongoose 2 + |
core count | 4 + |
designer | Samsung + |
first launched | February 23, 2017 + |
full page name | samsung/microarchitectures/m2 + |
instance of | microarchitecture + |
instruction set architecture | ARMv8 + |
manufacturer | Samsung + |
microarchitecture type | CPU + |
name | Mongoose 2 + |
phase-out | 2018 + |
pipeline stages | 14 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |