Editing samsung/microarchitectures/m2

{{samsung title|Mongoose 2 (M2)|arch}}
{{microarchitecture
|atype=CPU
|name=Mongoose 2
|designer=Samsung
|manufacturer=Samsung
|introduction=February 23, 2017
|phase-out=2018
|process=10 nm
|cores=4
|oooe=Yes
|speculative=Yes
|renaming=Yes
|decode=4-way
|isa=ARMv8
|l1i=64 KiB
|l1i per=core
|l1i desc=4-way set associative
|l1d=32 KiB
|l1d per=core
|l1d desc=8-way set associative
|l2=2 MiB
|l2 per=cluster
|l2 desc=16-way set associative
|predecessor=M1
|predecessor link=samsung/microarchitectures/m1
|successor=M3
|successor link=samsung/microarchitectures/m3
}}
'''Mongoose 2''' ('''M2''') is an [[ARM]] microarchitecture designed by [[Samsung]] for their consumer electronics serving as a successor to the {{\\|Mongoose 1}}.

== Process Technology ==
M2 was fabricated on Samsung's first generation [[10 nm process|10LPE (Low Power Early) process]].

== Compiler support ==
{| class="wikitable"
|-
! Compiler !! Arch-Specific || Arch-Favorable
|-
| [[GCC]] || <code>-mcpu=exynos-m2</code> || <code>-mtune=exynos-m2</code>
|-
| [[LLVM]] || <code>-mcpu=exynos-m2</code> || <code>-mtune=exynos-m2</code>
|}

== Architecture ==
=== Key changes from {{\\|Mongoose 1}} ===
* [[10 nm|10nm (10LPE) process]] (from [[14 nm]])
* Larger [[ROB]] (100, up from 96)
{{expand list}}

=== Block Diagram ===
==== Core Cluster Overview ====
<small>(Cluster identical to {{\\|Mongoose 1}})</small>

[[File:mongoose 1 soc block diagram.svg|500px]]

==== Individual Core ====
[[File:mongoose 2 block diagram.svg|900px]]

=== Memory Hierarchy ===
* Cache
** L1I Cache
*** 64 KiB, 4-way set associative
**** 128 B line size
**** per core
*** Parity-protected
** L1D Cache
*** 32 KiB, 8-way set associative
**** 64 B line size
**** per core
*** 4 cycles for fastest load-to-use
*** 16 B/cycle load bandwidth
*** 16 B/cycle store bandwidth
** L2 Cache
*** 2 MiB, 16-way set associative
**** 4x banks (512 KiB each)
*** Inclusive of L1
*** 22 cycles latency
*** 16 B/cycle/CPU bandwidth

Mongoose 1 TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB).

* TLBs
** ITLB
*** 256-entry
** DTLB
*** 32-entry
** STLB
*** 1,024-entry
*** Per core

* BPU
** 4K-entry main BTB
** 64-entry µBTB
** 64-entry return stack

== Core ==
The M2 core appears to be fairly identical to the {{\\|Mongoose 1|M1}}.

== All M2 Processors ==
<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable tc5 tc6 tc7">
{{comp table header|main|8:List of M2-based Processors}}
{{comp table header|main|6:Main processor|2:Integrated Graphics}}
{{comp table header|cols|Family|Launched|Arch|Cores|%Frequency|%Turbo|GPU|%Frequency}}
{{#ask: [[Category:microprocessor models by samsung]] [[microarchitecture::Mongoose 2]]
 |?full page name
 |?model number
 |?family
 |?first launched
 |?microarchitecture
 |?core count
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?integrated gpu
 |?integrated gpu base frequency
 |format=template
 |template=proc table 3
 |userparam=10
 |mainlabel=-
 |valuesep=,
}}
{{comp table count|ask=[[Category:microprocessor models by samsung]] [[microarchitecture::Mongoose 2]]}}
</table>
{{comp table end}}
codename	Mongoose 2 +
core count	4 +
designer	Samsung +
first launched	February 23, 2017 +
full page name	samsung/microarchitectures/m2 +
instance of	microarchitecture +
instruction set architecture	ARMv8 +
manufacturer	Samsung +
microarchitecture type	CPU +
name	Mongoose 2 +
phase-out	2018 +
pipeline stages	14 +
process	10 nm (0.01 μm, 1.0e-5 mm) +