Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "renesas/r-car/h3 (sip)"
(Created page with "{{renesas title|R-Car H3 (SiP}} {{mpu}} '''R-Car H3''' is a {{arch|64}} nona-core ARM SoC designed by Renesas for the automotive industry and introduced in 2016. T...") |
|||
| Line 1: | Line 1: | ||
| − | {{renesas title|R-Car H3 (SiP}} | + | {{renesas title|R-Car H3 (SiP)}} |
{{mpu}} | {{mpu}} | ||
'''R-Car H3''' is a {{arch|64}} [[nona-core]] [[ARM]] SoC designed by [[Renesas]] for the automotive industry and introduced in 2016. The H3 incorporates four {{armh|Cortex-A57}} cores, four {{armh|Cortex-A53}} cores, and a single {{armh|Cortex-R7}} core for real-time processing. This chip supports up to quad-channel LPDDR4-3200 memory. | '''R-Car H3''' is a {{arch|64}} [[nona-core]] [[ARM]] SoC designed by [[Renesas]] for the automotive industry and introduced in 2016. The H3 incorporates four {{armh|Cortex-A57}} cores, four {{armh|Cortex-A53}} cores, and a single {{armh|Cortex-R7}} core for real-time processing. This chip supports up to quad-channel LPDDR4-3200 memory. | ||
This model is an [[SiP]] variant of the {{\\|H3}} which include the DDR memory on-package. | This model is an [[SiP]] variant of the {{\\|H3}} which include the DDR memory on-package. | ||
Revision as of 03:26, 23 July 2017
Template:mpu R-Car H3 is a 64-bit nona-core ARM SoC designed by Renesas for the automotive industry and introduced in 2016. The H3 incorporates four Cortex-A57 cores, four Cortex-A53 cores, and a single Cortex-R7 core for real-time processing. This chip supports up to quad-channel LPDDR4-3200 memory.
This model is an SiP variant of the H3 which include the DDR memory on-package.
