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Difference between revisions of "renesas/r-car/e2"
< renesas‎ | r-car

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|series=2nd Gen
 
|series=2nd Gen
 
|frequency=1,000 MHz
 
|frequency=1,000 MHz
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|frequency 2=780 MHz
 
|isa=ARMv7
 
|isa=ARMv7
 
|isa family=ARM
 
|isa family=ARM
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|package module 1={{packages/renesas/fcbga-501}}
 
|package module 1={{packages/renesas/fcbga-501}}
 
}}
 
}}
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'''R-Car E2''' is an entry-level embedded [[tri-core]] SoC designed by [[Renesas]] for the automotive industry and introduced in late 2014. The E2 incorporates two {{armh|Cortex-A7}} cores operating at 1 GHz along with a {{renesas|SH-4A}} core operating at 780 MHz for real-time processing. This chip includes an [[Imagination Technologies|Imagination]] {{imgtec|PowerVR SGX540}} [[GPU]] operating at 260 MHz and supports up to 2 GiB of dual-channel DDR3-1333 memory.
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== Cache ==
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{{main|arm holdings/microarchitectures/cortex-a7#Memory_Hierarchy|l1=Cortex-A7 § Cache}}
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{{cache size
 +
|l1 cache=192 KiB
 +
|l1i cache=96 KiB
 +
|l1i break=3x32 KiB
 +
|l1d cache=96 KiB
 +
|l1d break=3x32 KiB
 +
|l2 cache=512 KiB
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|l2 break=1x512 KiB
 +
}}
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 +
== Memory controller ==
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{{memory controller
 +
|type=DDR3-1333
 +
|ecc=No
 +
|max mem=2 GiB
 +
|controllers=1
 +
|channels=2
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|width=32 bit
 +
|max bandwidth=9.93 GiB/s
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|bandwidth schan=4.97 GiB/s
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|bandwidth dchan=9.93 GiB/s
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}}
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== Expansions ==
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* Flash ROM and SRAM, Data bus width: 8 or 16 bits
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* USB 2.0 host interface × 2 ports (wPHY)
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* SD host interface × 3 ch (SDXC, UHS-I)
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* Multimedia card interface × 1 ch
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* I²C bus interface × 8 ch
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* Serial communication interface (SCIF) × 18 ch
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* Quad serial peripheral interface (QSPI) × 1 ch (for boot)
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* Clock-synchronized serial interface (MSIOF) × 3 ch (SPI/IIS)
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* Ethernet AVB controller (IEEE802.1BA/802.1AS/802.1Qav/IEEE1722, GMII/MII, without PHY)
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* Ethernet controller (IEEE802.3u, RMII, without PHY)
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 +
== Graphics ==
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{{integrated graphics
 +
| gpu                = PowerVR SGX540
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| designer            = Imagination Technologies
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| execution units    = 1
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| max displays        = 2
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| frequency          = 260 MHz
 +
}}
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 +
== Features ==
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{{arm features
 +
|thumb=No
 +
|thumb2=Yes
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|thumbee=Yes
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|vfpv1=No
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|vfpv2=No
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|vfpv3=No
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|vfpv3-d16=No
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|vfpv3-f16=No
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|vfpv4=Yes
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|vfpv4-d16=No
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|vfpv5=No
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|neon=Yes
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|jazelle=No
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|wmmx=No
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|wmmx2=No
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}}
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== Block Diagram ==
 +
::[[File:r-car e2 block.png|750px]]

Revision as of 16:22, 22 July 2017

Template:mpu R-Car E2 is an entry-level embedded tri-core SoC designed by Renesas for the automotive industry and introduced in late 2014. The E2 incorporates two Cortex-A7 cores operating at 1 GHz along with a SH-4A core operating at 780 MHz for real-time processing. This chip includes an Imagination PowerVR SGX540 GPU operating at 260 MHz and supports up to 2 GiB of dual-channel DDR3-1333 memory.

Cache

Main article: Cortex-A7 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$192 KiB
196,608 B
0.188 MiB
L1I$96 KiB
98,304 B
0.0938 MiB
3x32 KiB  
L1D$96 KiB
98,304 B
0.0938 MiB
3x32 KiB  
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  1x512 KiB  

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1333
Supports ECCNo
Max Mem2 GiB
Controllers1
Channels2
Width32 bit
Max Bandwidth9.93 GiB/s
10,168.32 MiB/s
10.662 GB/s
10,662.256 MB/s
0.0097 TiB/s
0.0107 TB/s
Bandwidth
Single 4.97 GiB/s
Double 9.93 GiB/s

Expansions

  • Flash ROM and SRAM, Data bus width: 8 or 16 bits
  • USB 2.0 host interface × 2 ports (wPHY)
  • SD host interface × 3 ch (SDXC, UHS-I)
  • Multimedia card interface × 1 ch
  • I²C bus interface × 8 ch
  • Serial communication interface (SCIF) × 18 ch
  • Quad serial peripheral interface (QSPI) × 1 ch (for boot)
  • Clock-synchronized serial interface (MSIOF) × 3 ch (SPI/IIS)
  • Ethernet AVB controller (IEEE802.1BA/802.1AS/802.1Qav/IEEE1722, GMII/MII, without PHY)
  • Ethernet controller (IEEE802.3u, RMII, without PHY)

Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR SGX540
DesignerImagination Technologies
Execution Units1Max Displays2
Frequency260 MHz
0.26 GHz
260,000 KHz

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
Thumb-2Thumb-2 Extension
ThumbEEThumb Execution Environment Extension
VFPv4Vector Floating Point (VFP) v4 Extension
NEONAdvanced SIMD extension

Block Diagram

r-car e2 block.png
Retrieved from "https://en.wikichip.org/w/index.php?title=renesas/r-car/e2&oldid=55851"
Facts about "R-Car E2 - Renesas"
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has ecc memory supportfalse +
integrated gpuPowerVR SGX540 +
integrated gpu base frequency260 MHz (0.26 GHz, 260,000 KHz) +
integrated gpu designerImagination Technologies +
integrated gpu execution units1 +
l1$ size192 KiB (196,608 B, 0.188 MiB) +
l1d$ size96 KiB (98,304 B, 0.0938 MiB) +
l1i$ size96 KiB (98,304 B, 0.0938 MiB) +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
max memory bandwidth9.93 GiB/s (10,168.32 MiB/s, 10.662 GB/s, 10,662.256 MB/s, 0.0097 TiB/s, 0.0107 TB/s) +
max memory channels2 +
supported memory typeDDR3-1333 +