Semiconductor & Computer Engineering
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| core count = 25 | | core count = 25 | ||
| thread count = 50 | | thread count = 50 | ||
| − | | max cpus = | + | | max cpus = 20,000 |
| max memory = | | max memory = | ||
| max memory addr = | | max memory addr = | ||
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'''Piton''' is a {{arch|64}} [[many-core microprocessor]] developed by [[Princeton]]'s Parallel Computing Group and announced in August of 2016. The [[massively parallel processor array|MPPA]] chip contains 25 modified [[OpenSPARC T1]] cores (an implementation of {{sparc|V9|SPARC V9}}). The chip, which was manufactured on [[IBM]]'s [[32 nm|32 nm SOI process]], operates at 1 GHz. The chip was presented On August 32 2016 at the [[Hot Chips]] 28. | '''Piton''' is a {{arch|64}} [[many-core microprocessor]] developed by [[Princeton]]'s Parallel Computing Group and announced in August of 2016. The [[massively parallel processor array|MPPA]] chip contains 25 modified [[OpenSPARC T1]] cores (an implementation of {{sparc|V9|SPARC V9}}). The chip, which was manufactured on [[IBM]]'s [[32 nm|32 nm SOI process]], operates at 1 GHz. The chip was presented On August 32 2016 at the [[Hot Chips]] 28. | ||
| + | |||
| + | == Architecture == | ||
| + | The chip is designed as a [[massively parallel processor array]], with 25 cores ("tiles") arranged as a grid 5 by 5. Each core is a modified [[OpenSPARC T1]] which implements {{sparc|V9|SPARC V9}} capable of booting a standard [[operating system|OS]]. Piton implements a 64-bit [[network on chip]] (NoC) interconnect made of 3 physical networks operating at 1 cycle/hop latency. | ||
| + | |||
| + | === Tiles === | ||
| + | Piton is made of an array of tiles in a grid of 5x5. Each tile is composed of a modified [[OpenSPARC T1]] core (+L1$), an L1.5 cache, L2 cache, a [[floating-point unit]] (FPU), a CPU Cache-Crossbar (CCX) arbiter, and three [[network on chip]] (NoC) routers. | ||
| + | |||
| + | ==== Cache ==== | ||
| + | Pitons uses a distributed write-back [[L2$]] model that implements a directory-based [[MESI protocol]] - adhering to OpenSPARC's total store order (TSO) model. Each tile contains 64 KB slice of the L2 cache and an attached cache directory. The L2 cache is inclusive of both the L1.5$ and the L1$. Note that the L1.5 is called as such because the [[OpenSPARC T1]] core already implements an 8 KB [[L1d$]] and 16 KB [[L1i$]] which are tightly coupled with the pipeline and was thus only modified to work in a scaleable multi-core environment. The L1.5$ acts as a middleman between the OpenSPARC T1's crossbar protocol and the Piton's NoC. It relays requests and replies to and from the core through CCX. | ||
| + | |||
| + | {{cache info | ||
| + | |l1i cache= | ||
| + | |l1i break= | ||
| + | |l1i desc= | ||
| + | |l1i extra= | ||
| + | |l1d cache=200 KB | ||
| + | |l1d break=25x8 KB | ||
| + | |l1d desc=4-way set associative | ||
| + | |l1d extra=(write-back, per tile) | ||
| + | |l2 cache=1.6 MB | ||
| + | |l2 break=25x64 KB | ||
| + | |l2 desc=4-way set associative | ||
| + | |l2 extra=(per tile) | ||
| + | |l3 cache= | ||
| + | |l3 break= | ||
| + | |l3 desc=16-way set associative | ||
| + | |l3 extra= | ||
| + | }} | ||
Revision as of 23:04, 28 August 2016
Template:mpu Piton is a 64-bit many-core microprocessor developed by Princeton's Parallel Computing Group and announced in August of 2016. The MPPA chip contains 25 modified OpenSPARC T1 cores (an implementation of SPARC V9). The chip, which was manufactured on IBM's 32 nm SOI process, operates at 1 GHz. The chip was presented On August 32 2016 at the Hot Chips 28.
Architecture
The chip is designed as a massively parallel processor array, with 25 cores ("tiles") arranged as a grid 5 by 5. Each core is a modified OpenSPARC T1 which implements SPARC V9 capable of booting a standard OS. Piton implements a 64-bit network on chip (NoC) interconnect made of 3 physical networks operating at 1 cycle/hop latency.
Tiles
Piton is made of an array of tiles in a grid of 5x5. Each tile is composed of a modified OpenSPARC T1 core (+L1$), an L1.5 cache, L2 cache, a floating-point unit (FPU), a CPU Cache-Crossbar (CCX) arbiter, and three network on chip (NoC) routers.
Cache
Pitons uses a distributed write-back L2$ model that implements a directory-based MESI protocol - adhering to OpenSPARC's total store order (TSO) model. Each tile contains 64 KB slice of the L2 cache and an attached cache directory. The L2 cache is inclusive of both the L1.5$ and the L1$. Note that the L1.5 is called as such because the OpenSPARC T1 core already implements an 8 KB L1d$ and 16 KB L1i$ which are tightly coupled with the pipeline and was thus only modified to work in a scaleable multi-core environment. The L1.5$ acts as a middleman between the OpenSPARC T1's crossbar protocol and the Piton's NoC. It relays requests and replies to and from the core through CCX.
| Cache Info [Edit Values] | ||
| L1D$ | 200 KB "KB" is not declared as a valid unit of measurement for this property. |
25x8 KB 4-way set associative (write-back, per tile) |
| L2$ | 1.6 MB "MB" is not declared as a valid unit of measurement for this property. |
25x64 KB 4-way set associative (per tile) |
| l1d$ description | 4-way set associative + |
| l2$ description | 4-way set associative + |
