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Difference between revisions of "princeton/piton"
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| − | '''Piton''' is a {{arch|64}} [[many-core microprocessor]] developed by [[Princeton]]'s Parallel Computing Group and announced in August of 2016. The [[massively parallel processor array|MPPA]] chip contains 25 modified [[OpenSPARC T1]] cores (an implementation of {{sparc|V9|SPARC V9}}). | + | {{mpu |
| + | | name = Piton | ||
| + | | no image = | ||
| + | | image = Princeton piton.png | ||
| + | | image size = | ||
| + | | caption = Piton face | ||
| + | | designer = Princeton | ||
| + | | manufacturer = IBM | ||
| + | | model number = | ||
| + | | part number = | ||
| + | | market = Server | ||
| + | | first announced = August 23, 2016 | ||
| + | | first launched = | ||
| + | | last order = | ||
| + | | last shipment = | ||
| + | |||
| + | | family = | ||
| + | | series = | ||
| + | | locked = | ||
| + | | frequency = 1000 MHz | ||
| + | | bus type = | ||
| + | | bus speed = 350 MHz | ||
| + | | bus rate = 2,800 MT/s | ||
| + | | clock multiplier = 2.85 | ||
| + | | cpuid = | ||
| + | | cpuid 2 = | ||
| + | |||
| + | | microarch = | ||
| + | | platform = | ||
| + | | chipset = | ||
| + | | core name = | ||
| + | | core family = | ||
| + | | core model = | ||
| + | | core stepping = | ||
| + | | process = 32 nm | ||
| + | | transistors = 460,000,000 | ||
| + | | technology = CMOS | ||
| + | | die size = 36mm² | ||
| + | | word size = 64 bit | ||
| + | | core count = 25 | ||
| + | | thread count = 50 | ||
| + | | max cpus = | ||
| + | | max memory = | ||
| + | | max memory addr = | ||
| + | |||
| + | | electrical = Yes | ||
| + | | power = | ||
| + | | v core = 0.9 V | ||
| + | | v core tolerance = | ||
| + | | v io = | ||
| + | | v io tolerance = | ||
| + | | sdp = | ||
| + | | tdp = | ||
| + | | ctdp down = | ||
| + | | ctdp down frequency = | ||
| + | | ctdp up = | ||
| + | | ctdp up frequency = | ||
| + | | temp min = | ||
| + | | temp max = | ||
| + | | tjunc min = | ||
| + | | tjunc max = | ||
| + | | tcase min = | ||
| + | | tcase max = | ||
| + | | tstorage min = | ||
| + | | tstorage max = | ||
| + | |||
| + | | packaging = Yes | ||
| + | | package 0 = QFP-208 | ||
| + | | package 0 type = QFP | ||
| + | | package 0 pins = 208 | ||
| + | | package 0 pitch = 0.5 mm | ||
| + | | package 0 width = 30.60 mm | ||
| + | | package 0 length = 30.60 mm | ||
| + | | package 0 height = 3.75 mm | ||
| + | | socket 0 = QFP-208 | ||
| + | | socket 0 type = QFP | ||
| + | }} | ||
| + | '''Piton''' is a {{arch|64}} [[many-core microprocessor]] developed by [[Princeton]]'s Parallel Computing Group and announced in August of 2016. The [[massively parallel processor array|MPPA]] chip contains 25 modified [[OpenSPARC T1]] cores (an implementation of {{sparc|V9|SPARC V9}}). The chip, which was manufactured on [[IBM]]'s [[32 nm|32 nm SOI process]], operates at 1 GHz. The chip was presented On August 32 2016 at the [[Hot Chips]] 28. | ||
Revision as of 22:15, 28 August 2016
Template:mpu Piton is a 64-bit many-core microprocessor developed by Princeton's Parallel Computing Group and announced in August of 2016. The MPPA chip contains 25 modified OpenSPARC T1 cores (an implementation of SPARC V9). The chip, which was manufactured on IBM's 32 nm SOI process, operates at 1 GHz. The chip was presented On August 32 2016 at the Hot Chips 28.
