Semiconductor & Computer Engineering
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Difference between revisions of "pezy/pezy-scx/pezy-scnp"
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| pcie revision = 3.0 | | pcie revision = 3.0 | ||
| − | | pcie lanes = | + | | pcie lanes = 24 |
| − | | pcie config = | + | | pcie config = x16 |
| − | | pcie config | + | | pcie config 2 = x8 |
| − | | pcie config | + | | pcie config 3 = x4 |
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| uart = Yes | | uart = Yes | ||
| gp io = Yes | | gp io = Yes | ||
}} | }} | ||
Revision as of 05:03, 23 June 2017
Template:mpu PEZY-SCnp (SC - Super Computer; np - New Package) is a revised version of the PEZY-SC model by PEZY introduced in may of 2016. The new model uses a slightly larger package, lower core voltage, slightly higher core frequency, and thus higher performance. The PEZY-SCnp is said to deliver 1.57 TFLOPS (double-precision). PEZY also upgraded the connections from PCIe Gen2 to Gen3. As with the PEZY-SC, the SCnp is also manufactured on TSMC's 28HPC+ (28 nm process).
Architecture
- Main article: PEZY-SC §Architecture
The PEZY-SCnp's architecture is identical to the PEZY-SC.
Cache
PEZY-SC's cache is separate from the ARM926's cache which has an L1$ of 32 KiB (2x) and 64 KiB L2$ (shared).
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Facts about "PEZY-SCnp - PEZY"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | PEZY-SCnp - PEZY#io + |
| has ecc memory support | true + |
| l1$ size | 3,072 KiB (3,145,728 B, 3 MiB) + |
| l1d$ description | per 2 processor elements + |
| l1d$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
| l1i$ description | per processor element + |
| l1i$ size | 2,048 KiB (2,097,152 B, 2 MiB) + |
| l2$ description | per city + |
| l2$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
| l3$ description | per prefecture + |
| l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
| max memory bandwidth | 127.156 GiB/s (130,207.744 MiB/s, 136.533 GB/s, 136,532.715 MB/s, 0.124 TiB/s, 0.137 TB/s) + |
| max memory channels | 8 + |
| max pcie lanes | 24 + |
| supported memory type | DDR4-2133 + |
