Semiconductor & Computer Engineering
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Difference between revisions of "pezy/pezy-scx/pezy-scnp"
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| − | '''PEZY-SCnp''' (SC - Super Computer; np - New Package) is a revised version of the {{pezy|PEZY-SC}} model by [[PEZY]] introduced in may of 2016. The new model uses a slightly larger package, lower core voltage, slightly higher core frequency, and thus higher performance. The PEZY-SCnp is said to deliver 1.57 TFLOPS (double-precision). PEZY also upgraded the connections from PCIe Gen2 to Gen3. PEZY-SC was As with the PEZ-SC, the SCnp is also manufactured on TSMC's 28HPC+ ([[28 nm process]]). | + | '''PEZY-SCnp''' (SC - '''Super Computer'''; np - '''New Package''') is a revised version of the {{pezy|PEZY-SC}} model by [[PEZY]] introduced in may of 2016. The new model uses a slightly larger package, lower core voltage, slightly higher core frequency, and thus higher performance. The PEZY-SCnp is said to deliver 1.57 TFLOPS (double-precision). PEZY also upgraded the connections from PCIe Gen2 to Gen3. PEZY-SC was As with the PEZ-SC, the SCnp is also manufactured on TSMC's 28HPC+ ([[28 nm process]]). |
== Architecture == | == Architecture == | ||
Revision as of 20:20, 6 September 2016
Template:mpu PEZY-SCnp (SC - Super Computer; np - New Package) is a revised version of the PEZY-SC model by PEZY introduced in may of 2016. The new model uses a slightly larger package, lower core voltage, slightly higher core frequency, and thus higher performance. The PEZY-SCnp is said to deliver 1.57 TFLOPS (double-precision). PEZY also upgraded the connections from PCIe Gen2 to Gen3. PEZY-SC was As with the PEZ-SC, the SCnp is also manufactured on TSMC's 28HPC+ (28 nm process).
Architecture
- Main article: PEZY-SC §Architecture
The PEZY-SCnp's architecture is identical to the PEZY-SC.
Cache
PEZY-SC's cache is separate from the ARM926's cache which has an L1$ of 32KB (2x) and 64KB L2$ (shared).
| Cache Info [Edit Values] | ||
| L1I$ | 2 MB "MB" is not declared as a valid unit of measurement for this property. |
1024x2 KB (per processor element) |
| L1D$ | 1 MB "MB" is not declared as a valid unit of measurement for this property. |
512x2 KB (per 2 processor elements) |
| L2$ | 4 MB "MB" is not declared as a valid unit of measurement for this property. |
4x2 MB (per city) |
| L3$ | 8 MB "MB" is not declared as a valid unit of measurement for this property. |
4x2 MB (per prefecture) |
Memory controller
| Integrated Memory Controller | |
| Type | DDR4-1866 |
| Controllers | 1 |
| Channels | 8 |
| Bandwidth (single) | 14,933 MB/s |
| Bandwidth (dual) | 29,866 MB/s |
| Bandwidth (quad) | 59,732 MB/s |
| Bandwidth (octa) | 119,464 MB/s |
