Semiconductor & Computer Engineering
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Difference between revisions of "pezy/pezy-scx/pezy-sc4"
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{{pezy title|PEZY-SC4}} | {{pezy title|PEZY-SC4}} | ||
| + | {{mpu | ||
| + | |future=Yes | ||
| + | |name=PEZY-SC4 | ||
| + | |no image=Yes | ||
| + | |designer=PEZY | ||
| + | |manufacturer=TSMC | ||
| + | |model number=PEZY-SC2 | ||
| + | |market=Supercomputer | ||
| + | |first announced=2016 | ||
| + | |first launched=2020 | ||
| + | |frequency=1,600 MHz | ||
| + | |process=5 nm | ||
| + | |technology=CMOS | ||
| + | |die area=740 mm² | ||
| + | |core count=16,192 | ||
| + | |power=640 W | ||
| + | |v core=0.55 V | ||
| + | }} | ||
'''PEZY-SC4''' ('''PEZY Super Computer 4''') is fifth generation [[many-core microprocessor]] planned by [[PEZY]]. The SC4 is planned to have 16,192 cores, twice as many cores as its predecessor. | '''PEZY-SC4''' ('''PEZY Super Computer 4''') is fifth generation [[many-core microprocessor]] planned by [[PEZY]]. The SC4 is planned to have 16,192 cores, twice as many cores as its predecessor. | ||
Revision as of 06:05, 23 June 2017
Template:mpu PEZY-SC4 (PEZY Super Computer 4) is fifth generation many-core microprocessor planned by PEZY. The SC4 is planned to have 16,192 cores, twice as many cores as its predecessor.
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Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release. |
Memory controller
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Integrated Memory Controller
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Integrated Memory Controller
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Facts about "PEZY-SC4 - PEZY"
| has ecc memory support | true + and false + |
| max memory bandwidth | 119.2 GiB/s (122,060.8 MiB/s, 127.99 GB/s, 127,990.025 MB/s, 0.116 TiB/s, 0.128 TB/s) + and 22,886.4 GiB/s (23,435,673.6 MiB/s, 24,574.085 GB/s, 24,574,084.881 MB/s, 22.35 TiB/s, 24.574 TB/s) + |
| max memory channels | 4 + and 8 + |
| supported memory type | DDR5-4000 + |
