Editing pezy/pezy-scx

{{pezy title|PEZY-SCx}}
{{ic family
| title             = PEZY-SCx
| image             = 
| caption           = 
| no image          = Yes
| developer         = PEZY Computing
| manufacturer      = TSMC
| type              = Microprocessors
| first announced   = 2014
| first launched    = 2014
| arch              = Many-core architecture
| isa               = 
| microarch         = 
| word              = 
| proc              = 28 nm
| proc 2            = 16 nm
| proc 3            = 7 nm
| proc 4            = 5 nm
| tech              = CMOS
| clock min         = 733 MHz
| clock max         = 1,600 MHz
| package           = 
| socket            = 

| succession       = 
| predecessor      = 
| predecessor link = 
| successor        = 
| successor link   = 
}}
'''PEZY-SCx''' ('''PEZY-S'''uper'''C'''omputer'''x''') is a family of [[many-core microprocessor]]s designed by [[PEZY]]. Those processors power many of [[Japan]]'s most efficient supercomputers.

== Overview ==
PEZY-SCx is a family of high-performance, low-power many-core microprocessors designed by [[PEZY]] for a series of supercomputer developed in [[Japan]]. PEZY collaborates closely with ExaScaler, a company that provides immersion cooling systems. Together, they have developed a series of supercomputers called [[ZettaScaler]].

=== Architecture ===
The basic architecture of all the PEZY-SCx chips is fairly similar. At the heart is the Processing Element. Depending on the model, 1000s of those PEs are then integrated on a single [[die]].

The PEZY-SCx are designed as accelerators, that is, the a host processor (typically an [[Intel]] {{intel|Xeon E5}}) off-loads the PEZY-SC code to execute. Those chips support OpenCL-like programming called PZCL.

====  Processing Element (PE) ====
[[File:pezy-sc pe.svg|right|200px]]
The [[physical core|cores]] are called the '''processing elements''' ('''PE'''). The PEs are designed to be very simple [[RISC]] cores that are confgured as [[MIMD]] although in principle each PE can run different workloads. Each PE is a 16-stage [[in-order]] [[superscalar]] capable of issuing two instructions per cycle with [[out-of-order]] completion whenever possible supporting 8-way fine-grain [[simultaneous multithreading]]. A processing element supports 8-way SMT with dedicated register files for each thread. Threads are are interleaved each cycle with switching done to reduce [[forwarding]] and in order mitigate the lack of [[branch prediction]]. Explicit switching of active threads is also done in order to hide high latency operations. 

The instruction set architecture implemented is a proprietary one designed by PEZY. The instruction set supports various operations such as data flashing, synchronization, acquisition of IDs, and thread switching. Each PE has an ID which is used by the code to track processes. The PEs do not maintain [[cache-coherency]] and there is no per-PE [[data cache]]. Complex instructions are processed by the Special Function Units (SFU) located in each city. A fair amount of sacrifices were made in order to ensure the cores remain small enough so that a large amount of them can be packed into a small area

==== Village & City ====
For every pair of PEs is 2 KiB of [[level 1 data cache]]. Each '''City''' is made of 64 KiB of [[L2 cache]], a number of special function units, and 4 smaller blocks called "Villages". A '''village''' consists of four processing elements. Each city also contains a Special Function Unit (SFU) which is used to execute complex instructions.

::[[File:pezy-sc city.svg|450px]]

== Models ==
The origin of the PEZY-SCx family is the {{pezy|PEZY-1}}, a 512-core chip.

=== 1st generation ===
{{main|pezy/pezy-scx/pezy-sc|l1=PEZY-SC}}
The first series of supercomputers, [[ZettaScaler#ZettaScaler-1.x|ZettaScaler-1.x]], were based on the {{\\|PEZY-SC}}. The {{\\|PEZY-SC}} featured four "Prefecture", each consisting of 16 cities for a total of 256 PEs per Prefecture along with 2 MiB of [[L3 cache]]. This chip had four such Prefecture units for a total of 1,024 [[physical core|cores]] and 8,192 [[logical cores|threads]]. Operating at 733 MHz, this chip was capable of 3 TFLOPS ([[single-precision]]) and 1.5 TFLOPS ([[double-precision]]).


: [[File:pezy-sc main block.svg|600px]]

=== 2nd generation ===
{{main|pezy/pezy-scx/pezy-sc2|l1=PEZY-SC2}}
The second series of supercomputers, [[ZettaScaler#ZettaScaler-2.x|ZettaScaler-2.x]], were based on the {{\\|PEZY-SC2}}.

: [[File:pezy-sc2 main block.svg|600px]]

=== future generations ===
PEZY has laid out future generations based on [[TSMC]]'s [[7nm]] and [[5nm]] processes.

== Summary ==
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{{comp table start}}
<table class="comptable sortable tc4">
{{comp table header|main|8:List of PEZY-SCx Processors}}
{{comp table header|main|5:Main Features|3:Performance}}
{{comp table header|cols|Process|Launched|Cores|Threads|Die|%Frequency|FLOPS (SP)|FLOPS (DP)}}
{{#ask: [[Category:microprocessor models by pezy]] [[family::PEZY-SCx]]
 |?full page name
 |?model number
 |?process
 |?first launched
 |?core count
 |?thread count
 |?die area
 |?base frequency#MHz
 |?peak flops (single-precision)#TFLOPS
 |?peak flops (double-precision)#TFLOPS
 |format=template
 |template=proc table 3
 |userparam=10
 |mainlabel=-
 |sort=process,model number
}}
{{comp table count|ask=[[Category:microprocessor models by pezy]] [[family::PEZY-SCx]]}}
</table>
{{comp table end}}

== See also ==
* Intel {{intel|Xeon Phi}}

== Bibliography ==
* IEEE Cool Chips XVIII Symposium 2015.
* JSICR HPC (2015-HPC-152) "Suiren（睡蓮）による計算科学アプリケーションの性能評価" (Performance evaluation of scientific applications on Suiren System)
* The Fifth International Symposium on Computing and Networking 2017 (CANDAR'17). Keynote address.

[[category:supercomputing in japan]]
designer	PEZY Computing +
first announced	2014 +
first launched	2014 +
full page name	pezy/pezy-scx +
instance of	microprocessor family +
main designer	PEZY Computing +
manufacturer	TSMC +
name	PEZY-SCx +
process	28 nm (0.028 μm, 2.8e-5 mm) +, 16 nm (0.016 μm, 1.6e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 5 nm (0.005 μm, 5.0e-6 mm) +
technology	CMOS +