Semiconductor & Computer Engineering
From WikiChip
Editing nvidia/microarchitectures/denver
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
| Latest revision | Your text | ||
| Line 1: | Line 1: | ||
| − | {{nvidia title| | + | {{nvidia title|denver}} |
{{microarchitecture | {{microarchitecture | ||
| − | |atype=CPU | + | | atype = CPU |
| − | |name=Denver | + | | name = Denver |
| − | |designer=Nvidia | + | | designer = Nvidia |
| − | |manufacturer=TSMC | + | | manufacturer = TSMC |
| − | |introduction=2014 | + | | introduction = 2014 |
| − | |process=28 nm | + | | phase-out = |
| − | |process 2=16 nm | + | | process = 28 nm |
| − | |cores=2 | + | | process 2 = 16 nm |
| − | | | + | | cores = 2 |
| − | + | | cores 2 = 4 | |
| − | + | | cores N = | |
| − | |||
| − | |||
| − | |||
| − | |||
| − | | | ||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | + | | type = <!-- e.g. "Superscalar" --> | |
| + | | type 2 = | ||
| + | | type N = | ||
| + | | oooe = No | ||
| + | | speculative = <!-- Yes or No only --> | ||
| + | | renaming = <!-- Yes or No only --> | ||
| + | | stages = <!-- ONLY IF FIXED SIZE, otherwise use below for range --> | ||
| + | | stages min = | ||
| + | | stages max = | ||
| + | | decode = 2-way | ||
| − | + | | isa = ARMv8 | |
| + | | isa 2 = | ||
| + | | isa N = | ||
| + | | feature = | ||
| + | | extension = | ||
| + | | extension 2 = | ||
| + | | extension N = | ||
| − | + | | l1i = 128 KiB | |
| − | | | + | | l1i per = core |
| − | |- | + | | l1i desc = 4-way set associative |
| − | | | + | | l1d = 64 KiB |
| − | | | + | | l1d per = core |
| − | | | + | | l1d desc = 4-way set associative |
| + | | l2 = 2 MiB | ||
| + | | l2 per = core | ||
| + | | l2 desc = 16-way set associative | ||
| + | | l3 = | ||
| + | | l3 per = | ||
| + | | l3 desc = | ||
| − | === | + | | core name = |
| − | + | | core name 2 = | |
| + | | core name N = | ||
| − | + | | predecessor = | |
| − | + | | predecessor link = | |
| − | + | | successor = | |
| − | + | | successor link = | |
| − | + | | successor 2 = | |
| − | + | | successor 2 link = | |
| − | + | | successor N = | |
| − | + | | successor N link = | |
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | | | ||
| − | | | ||
| − | | | ||
| − | | | ||
| − | | | ||
| − | | | ||
| − | |||
| − | |||
| − | | | ||
| − | | | ||
}} | }} | ||
| + | '''Denver''' is a CPU microarchitecture from [[Nvidia]] introduced in 2014, capable of executing ARMv8 code natively and with help of dynamic code optimization. Native ARM decoder can issue up to 2 instructions per cycle, and up to 7 micro-operations are started per cycle when dynamic code translation is used. | ||
| − | + | == Architecture == | |
| − | |||
| − | |||
| − | |||
| − | == | ||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
== Products == | == Products == | ||
| − | Denver is used in | + | Denver is used in Tegra K1-64. |
| − | |||
| − | |||
== Die == | == Die == | ||
| Line 158: | Line 114: | ||
== References == | == References == | ||
* NVIDIA’S FIRST CPU IS A WINNER. Denver Uses Dynamic Translation to Outperform Mobile Rivals. - Linley Gwennap (August 18, 2014) <!-- Nvidia_Denverreprint.pdf --> | * NVIDIA’S FIRST CPU IS A WINNER. Denver Uses Dynamic Translation to Outperform Mobile Rivals. - Linley Gwennap (August 18, 2014) <!-- Nvidia_Denverreprint.pdf --> | ||
| − | + | ||
| − | |||
| − | |||
[[category:nvidia]] | [[category:nvidia]] | ||
Facts about "Denver - Microarchitectures - Nvidia"
| codename | Denver + |
| core count | 2 + |
| designer | Nvidia + |
| first launched | 2014 + |
| full page name | nvidia/microarchitectures/denver + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv8 + |
| l1$ size | 384 KiB (393,216 B, 0.375 MiB) + |
| l1d$ description | 4-way set associative + |
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Denver + |
| process | 28 nm (0.028 μm, 2.8e-5 mm) + and 16 nm (0.016 μm, 1.6e-5 mm) + |
