From WikiChip
Editing nvidia/microarchitectures/carmel
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 9: | Line 9: | ||
|cores=8 | |cores=8 | ||
|type=Superscalar | |type=Superscalar | ||
+ | |oooe=Yes | ||
+ | |speculative=Yes | ||
+ | |renaming=Yes | ||
|isa=ARMv8 | |isa=ARMv8 | ||
|feature=RAS | |feature=RAS | ||
Line 18: | Line 21: | ||
|predecessor link=nvidia/microarchitectures/denver 2 | |predecessor link=nvidia/microarchitectures/denver 2 | ||
}} | }} | ||
− | + | Carmel is a the successor to {{\\|Denver 2}}, an [[ARM]] microarchitecture for [[Nvidia]]'s {{nvidia|Tegra}} series of [[SoCs]]. | |
− | |||
− | |||
− | |||
== Architecture == | == Architecture == | ||
− | Nvidia disclosed very few details regarding Carmel | + | Nvidia disclosed very few details regarding Carmel. |
− | + | * [[12 nm]] (12FF) | |
− | * [[12 nm]] ( | + | * ARMv8.2 (Only AArch64) |
− | * ARMv8.2 | ||
** ARM RAS standard support | ** ARM RAS standard support | ||
− | * | + | * Eight-core cluster |
+ | ** 4x Core duplexes | ||
=== Memory Hierarchy === | === Memory Hierarchy === | ||
* Cache | * Cache | ||
− | |||
** L1 | ** L1 | ||
** L2 | ** L2 | ||
Line 43: | Line 42: | ||
**** Shared by entire cluster | **** Shared by entire cluster | ||
**** Exclusive | **** Exclusive | ||
− | |||
− | |||
− | |||
− | |||
== Overview == | == Overview == | ||
Carmel is a CPU microarchitecture designed by Nvidia for their SoCs. The design consists of an 8-core cluster made of 4 core duplexes. The entire complex has [[cache coherency]] as well as an I/O coherent memory subsystem which is designed for communication with the various other accelerators on their SoCs such as the vision accelerator, deep learning accelerator, multimedia engine, and the GPU. | Carmel is a CPU microarchitecture designed by Nvidia for their SoCs. The design consists of an 8-core cluster made of 4 core duplexes. The entire complex has [[cache coherency]] as well as an I/O coherent memory subsystem which is designed for communication with the various other accelerators on their SoCs such as the vision accelerator, deep learning accelerator, multimedia engine, and the GPU. | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
== Die == | == Die == | ||
Line 68: | Line 53: | ||
* ~62.25 mm² die size area | * ~62.25 mm² die size area | ||
− | :[[File:nvidia carmel complex.png | + | :[[File:nvidia carmel complex.png|600px]] |
Facts about "Carmel - Microarchitectures - Nvidia"
codename | Carmel + |
core count | 8 + |
designer | Nvidia + |
first launched | January 7, 2018 + |
full page name | nvidia/microarchitectures/carmel + |
instance of | microarchitecture + |
instruction set architecture | ARMv8 + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Carmel + |
process | 12 nm (0.012 μm, 1.2e-5 mm) + |