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|cores=8 | |cores=8 | ||
|type=Superscalar | |type=Superscalar | ||
+ | |oooe=Yes | ||
+ | |speculative=Yes | ||
+ | |renaming=Yes | ||
|isa=ARMv8 | |isa=ARMv8 | ||
|feature=RAS | |feature=RAS | ||
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|predecessor link=nvidia/microarchitectures/denver 2 | |predecessor link=nvidia/microarchitectures/denver 2 | ||
}} | }} | ||
− | + | Carmel is a the successor to {{\\|Denver 2}}, an [[ARM]] microarchitecture for [[Nvidia]]'s {{nvidia|Tegra}} series of [[SoCs]]. | |
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== Architecture == | == Architecture == | ||
− | Nvidia disclosed very few details regarding Carmel | + | Nvidia disclosed very few details regarding Carmel. |
− | + | * [[12 nm]] (12FF) | |
− | * [[12 nm]] ( | + | * ARMv8.2 (Only AArch64) |
− | * ARMv8.2 | ||
** ARM RAS standard support | ** ARM RAS standard support | ||
− | * | + | * Eight-core cluster |
+ | ** 4x Core duplexes | ||
=== Memory Hierarchy === | === Memory Hierarchy === | ||
* Cache | * Cache | ||
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** L1 | ** L1 | ||
** L2 | ** L2 | ||
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**** Shared by entire cluster | **** Shared by entire cluster | ||
**** Exclusive | **** Exclusive | ||
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== Bibliography == | == Bibliography == | ||
* IEEE Hot Chips 30 Symposium (HCS) 2018. | * IEEE Hot Chips 30 Symposium (HCS) 2018. |
Facts about "Carmel - Microarchitectures - Nvidia"
codename | Carmel + |
core count | 8 + |
designer | Nvidia + |
first launched | January 7, 2018 + |
full page name | nvidia/microarchitectures/carmel + |
instance of | microarchitecture + |
instruction set architecture | ARMv8 + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Carmel + |
process | 12 nm (0.012 μm, 1.2e-5 mm) + |