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File:sx-aurora chip (annotated).png | File:sx-aurora chip (annotated).png | ||
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The package itself is very big at 60 mm x 60 mm. The VE processor die itself is 15 mm x 33 mm with a very large interposer with a total Si area of 1,235 mm² (32.5 mm x 38 mm). | The package itself is very big at 60 mm x 60 mm. The VE processor die itself is 15 mm x 33 mm with a very large interposer with a total Si area of 1,235 mm² (32.5 mm x 38 mm). | ||
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:[[File:nec sx-aurora tsubasa package.svg|800px]] | :[[File:nec sx-aurora tsubasa package.svg|800px]] | ||
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Though other chips have reached very large interposer sizes before, the SX-Aurora is the first 6 HBM2 implementation. It uses the second-generation [[CoWoS]] packaging technology ([[CoWoS-XL2]]) to exceed the [[reticle size]] through the use of mask stitching. | Though other chips have reached very large interposer sizes before, the SX-Aurora is the first 6 HBM2 implementation. It uses the second-generation [[CoWoS]] packaging technology ([[CoWoS-XL2]]) to exceed the [[reticle size]] through the use of mask stitching. | ||
+ | :[[File:sx-aurora-package-xsection.svg|800px]] | ||
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== All SX-Aurora Chips == | == All SX-Aurora Chips == |
Facts about "SX-Aurora - Microarchitectures - NEC"
codename | SX-Aurora + |
core count | 8 + |
designer | NEC + |
first launched | 2018 + |
full page name | nec/microarchitectures/sx-aurora + |
instance of | microarchitecture + |
manufacturer | TSMC + |
name | SX-Aurora + |
pipeline stages | 8 + |