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== History == | == History == | ||
− | The original SHAVE architecture was designed primarily for the [[hardware acceleration|acceleration]] of game physics. Low demand for expensive physics acceleration in smartphones has forced | + | The original SHAVE architecture was designed primarily for the [[hardware acceleration|acceleration]] of game physics. Low demand for expensive physics acceleration in smartphones has forced to re-focused on image and vision processing. Their architecture was versatile enough that it allowed for fairly simple modification to target machine vision processing. |
== Process Technology == | == Process Technology == | ||
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The entire chip also has a share 128 KiB of L2 cache and a integrated [[DDR2]] [[integrated memory controller|memory controller]] which is connected to an on-package stacked 8-64 MiB of [[SDRAM]]. | The entire chip also has a share 128 KiB of L2 cache and a integrated [[DDR2]] [[integrated memory controller|memory controller]] which is connected to an on-package stacked 8-64 MiB of [[SDRAM]]. | ||
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+ | === Inter-core communication === | ||
+ | This architecture does not have support for hardware synchronization primitives, however it does have a light communication system. | ||
+ | |||
+ | Each of the SHAVE cores has a small arbitration messaging [[queue]] consisting of four entries of 64-bit words which is only accessibly (read-wise) from that core. Each SHAVE core can send a message to any other core. When this happens the message is pushed onto that core's queue. If that core's queue is full, the sender will stall. This allows for very efficient SHAVE-SHAVE synchronization and communication without using any shared memory techniques. | ||
+ | |||
+ | It's worth noting that the control/management [[LEON3]] [[SPARC]] core does not have access to this communication system. | ||
=== Bandwidth === | === Bandwidth === | ||
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:[[File:movidius shave v2.0 sparse data support.png|700px]] | :[[File:movidius shave v2.0 sparse data support.png|700px]] | ||
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== Performance claims == | == Performance claims == | ||
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== Package == | == Package == | ||
[[File:myriad 1 bga.png|right|200px]] | [[File:myriad 1 bga.png|right|200px]] | ||
− | Movidius packaged those chips in an 8x8 mm [[BGA]] package with 225 [[solder ball|balls]]. The die is then | + | Movidius packaged those chips in an 8x8 mm [[BGA]] package with 225 [[solder ball|balls]]. The die is then bumpped on top of a custom [[FR-4 substrate]]. The SDRAM is then [[wire bond|wire bond]] on top of the Myriad die. |
:[[File:myriad package diagram.svg|600px]] | :[[File:myriad package diagram.svg|600px]] | ||
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− | :[[File:myriad 1 (shave v2.0) die shot.png | + | :[[File:myriad 1 (shave v2.0) die shot.png|600px]] |
:[[File:myriad 1 (shave v2.0) die shot (annotated).png|600px]] | :[[File:myriad 1 (shave v2.0) die shot (annotated).png|600px]] | ||
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== References == | == References == | ||
* Some information was obtained directly from Movidius | * Some information was obtained directly from Movidius | ||
* HotChips 23 (HC23), 2011 | * HotChips 23 (HC23), 2011 |
Facts about "SHAVE v2.0 - Microarchitectures - Intel Movidius"
codename | SHAVE v2.0 + |
designer | Movidius + |
first launched | 2011 + |
full page name | movidius/microarchitectures/shave v2.0 + |
instance of | microarchitecture + |
instruction set architecture | SHAVE + and SPARC v8 + |
manufacturer | TSMC + |
name | SHAVE v2.0 + |
phase-out | 2014 + |
process | 65 nm (0.065 μm, 6.5e-5 mm) + |