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The entire chip also has a share 128 KiB of L2 cache and a integrated [[DDR2]] [[integrated memory controller|memory controller]] which is connected to an on-package stacked 8-64 MiB of [[SDRAM]]. | The entire chip also has a share 128 KiB of L2 cache and a integrated [[DDR2]] [[integrated memory controller|memory controller]] which is connected to an on-package stacked 8-64 MiB of [[SDRAM]]. | ||
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+ | === Inter-core communication === | ||
+ | This architecture does not have support for hardware synchronization primitives, however it does have a light communication system. | ||
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+ | Each of the SHAVE cores has a small arbitration messaging [[queue]] consisting of four entries of 64-bit words which is only accessibly (read-wise) from that core. Each SHAVE core can send a message to any other core. When this happens the message is pushed onto that core's queue. If that core's queue is full, the sender will stall. This allows for very efficient SHAVE-SHAVE synchronization and communication without using any shared memory techniques. | ||
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+ | It's worth noting that the control/management [[LEON3]] [[SPARC]] core does not have access to this communication system. | ||
=== Bandwidth === | === Bandwidth === | ||
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:[[File:movidius shave v2.0 sparse data support.png|700px]] | :[[File:movidius shave v2.0 sparse data support.png|700px]] | ||
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== Performance claims == | == Performance claims == |
Facts about "SHAVE v2.0 - Microarchitectures - Intel Movidius"
codename | SHAVE v2.0 + |
designer | Movidius + |
first launched | 2011 + |
full page name | movidius/microarchitectures/shave v2.0 + |
instance of | microarchitecture + |
instruction set architecture | SHAVE + and SPARC v8 + |
manufacturer | TSMC + |
name | SHAVE v2.0 + |
phase-out | 2014 + |
process | 65 nm (0.065 μm, 6.5e-5 mm) + |