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== History == | == History == | ||
− | The original SHAVE architecture was designed primarily for the [[hardware acceleration|acceleration]] of game physics. Low demand for expensive physics acceleration in smartphones has forced | + | The original SHAVE architecture was designed primarily for the [[hardware acceleration|acceleration]] of game physics. Low demand for expensive physics acceleration in smartphones has forced to re-focused on image and vision processing. Their architecture was versatile enough that it allowed for fairly simple modification to target machine vision processing. |
== Process Technology == | == Process Technology == | ||
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=== Execution Units === | === Execution Units === | ||
[[File:shave v2 eus.png|right|400px]] | [[File:shave v2 eus.png|right|400px]] | ||
− | The three major arithmetic execution units are the vector arithmetic unit (VAU), the scalar arithmetic unit (SAU), and the integer arithmetic unit (IAU) | + | The three major arithmetic execution units are the vector arithmetic unit (VAU), the scalar arithmetic unit (SAU), and the integer arithmetic unit (IAU). |
The '''integer arithmetic unit''' ('''IAU''') performs all arithmetic instructions that operate on 32-bit integer numbers and access the IRF. The '''scalar arithmetic unit''' ('''SAU''') is far more versatile and can perform all [[integer]] (8-32 bit) and [[floating point]] (HP/FP) operations. The '''vector arithmetic unit''' ('''VAU''') supports 128-bit vector operations of all the integer (8-32 bit) and floating point (HP/FP) types. Since those operations can be done at in the same cycle, it's possible to perform combination of the two in order to do various DSP-like operations such as matrix switching. | The '''integer arithmetic unit''' ('''IAU''') performs all arithmetic instructions that operate on 32-bit integer numbers and access the IRF. The '''scalar arithmetic unit''' ('''SAU''') is far more versatile and can perform all [[integer]] (8-32 bit) and [[floating point]] (HP/FP) operations. The '''vector arithmetic unit''' ('''VAU''') supports 128-bit vector operations of all the integer (8-32 bit) and floating point (HP/FP) types. Since those operations can be done at in the same cycle, it's possible to perform combination of the two in order to do various DSP-like operations such as matrix switching. | ||
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Each SHAVE core has two [[load-store units]], each is capable of doing a single 64-bit operation per cycle from the SRAM tile. | Each SHAVE core has two [[load-store units]], each is capable of doing a single 64-bit operation per cycle from the SRAM tile. | ||
− | Each SHAVE core has a local 128 KiB slice of SRAM the LSU operates on | + | Each SHAVE core has a local 128 KiB slice of SRAM the LSU operates on. The cache is split between [[instruction cache|instruction]] and [[data cache|data]]. The exact amount is software configurable with a granularity of 8 KiB intervals. Each local cache tile is directly linked to two of its closest neighbors (presumably to the cores located to the west and to the east), allowing for zero-penalty accesses from those memory banks as well. For cache tiles located further on do have a slight latency penalty. Movidius noted that most of the software they've tested does almost all of its communication with its neighboring cores, allowing them to take advantage of this. |
The entire chip also has a share 128 KiB of L2 cache and a integrated [[DDR2]] [[integrated memory controller|memory controller]] which is connected to an on-package stacked 8-64 MiB of [[SDRAM]]. | The entire chip also has a share 128 KiB of L2 cache and a integrated [[DDR2]] [[integrated memory controller|memory controller]] which is connected to an on-package stacked 8-64 MiB of [[SDRAM]]. | ||
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:[[File:movidius shave v2.0 sparse data support.png|700px]] | :[[File:movidius shave v2.0 sparse data support.png|700px]] | ||
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== Performance claims == | == Performance claims == | ||
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== Package == | == Package == | ||
[[File:myriad 1 bga.png|right|200px]] | [[File:myriad 1 bga.png|right|200px]] | ||
− | Movidius packaged those chips in an 8x8 mm [[BGA]] package with 225 [[solder ball|balls]]. The die is then | + | Movidius packaged those chips in an 8x8 mm [[BGA]] package with 225 [[solder ball|balls]]. The die is then bumpped on top of a custom [[FR-4 substrate]]. The SDRAM is then [[wire bond|wire bond]] on top of the Myriad die. |
:[[File:myriad package diagram.svg|600px]] | :[[File:myriad package diagram.svg|600px]] | ||
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− | :[[File:myriad 1 (shave v2.0) die shot.png | + | :[[File:myriad 1 (shave v2.0) die shot.png|600px]] |
:[[File:myriad 1 (shave v2.0) die shot (annotated).png|600px]] | :[[File:myriad 1 (shave v2.0) die shot (annotated).png|600px]] | ||
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== References == | == References == | ||
* Some information was obtained directly from Movidius | * Some information was obtained directly from Movidius | ||
* HotChips 23 (HC23), 2011 | * HotChips 23 (HC23), 2011 |
Facts about "SHAVE v2.0 - Microarchitectures - Intel Movidius"
codename | SHAVE v2.0 + |
designer | Movidius + |
first launched | 2011 + |
full page name | movidius/microarchitectures/shave v2.0 + |
instance of | microarchitecture + |
instruction set architecture | SHAVE + and SPARC v8 + |
manufacturer | TSMC + |
name | SHAVE v2.0 + |
phase-out | 2014 + |
process | 65 nm (0.065 μm, 6.5e-5 mm) + |