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| | |manufacturer=TSMC | | |manufacturer=TSMC |
| | |introduction=2011 | | |introduction=2011 |
| − | |phase-out=2014
| + | |type=VLIW |
| − | |process=65 nm
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| − | |type=VLLIW | |
| − | |isa=SHAVE
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| − | |isa 2=SPARC v8
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| − | |l1=1 KiB
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| − | |l1 per=core
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| − | |l2=128 KiB
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| − | |l2 per=chip
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| − | |l2 desc=2-way set associative
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| − | |side cache=8-64 MiB SDRAM
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| − | |side cache per=chip
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| − | |predecessor=SHAVE v1.0
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| − | |predecessor link=movidius/microarchitectures/shave_v1.0
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| − | |successor=SHAVE v3.0
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| − | |successor link=movidius/microarchitectures/shave_v3.0
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| | }} | | }} |
| | '''Streaming Hybrid Architecture Vector Engine v2.0''' ('''SHAVE v2.0''') is an accelerator microarchitecture designed by [[Movidius]] for their vision processors. SHAVE-based products are branded as the {{movidius|Myriad}} family of vision processors. | | '''Streaming Hybrid Architecture Vector Engine v2.0''' ('''SHAVE v2.0''') is an accelerator microarchitecture designed by [[Movidius]] for their vision processors. SHAVE-based products are branded as the {{movidius|Myriad}} family of vision processors. |
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| | == History == | | == History == |
| − | The original SHAVE architecture was designed primarily for the [[hardware acceleration|acceleration]] of game physics. Low demand for expensive physics acceleration in smartphones has forced a re-focus on image and vision processing. Their architecture was versatile enough that it allowed for fairly simple modification to target machine vision processing. | + | The original SHAVE architecture was designed primarily for the [[hardware acceleration|acceleration]] of game physics. Low demand for expensive physics acceleration in smartphones has forced to re-focused on image and vision processing. Their architecture was versatile enough that it allowed for fairly simple modification to target machine vision processing. |
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| | == Process Technology == | | == Process Technology == |
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| | == Core == | | == Core == |
| − | The underlying concept behind the SHAVE core is extracting significant [[data-level parallelism]]. Each SHAVE core is a [[variable-length very long instruction word]] (VLLIW) processor that can operates on native 32-bit [[integer]] and 128-bit [[vector]] values. Each core incorporates a number of different types of [[register files]] as well as a large set of execution units that make use of the multiple register files with a large number of ports in order to operate on a relatively big set of values at once.
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| − | Every SHAVE core resides on an independent power island. Although we were not able to verify this, presumably you can enable and disable cores based on your power requirements through software.
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| − | === Register Files ===
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| − | There are three register files: Integer Register File (IRF), Scalar Register File (SRF), Vector Register File (VRF).
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| − | The SHAVE's integer register file (IRF) has 17 ports in order enable a large set of parallel data operations each cycle. The IRF has 32 entries of 32-bit integers which are predominantly operated on by the IAU and the SAU. In addition to the IRF is the scalar register file (SRF) which has another set of 32 entries of 32-bit integers. The reason for the second register is to allow the SHAVE to do various three-operand operations and generate predicates for the execution units.
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| − | The SHAVE core also has a dedicated vector register file (VRF) which contains 32 entries, each 128-bit wide.
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| − | === Execution Units ===
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| − | [[File:shave v2 eus.png|right|400px]]
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| − | The three major arithmetic execution units are the vector arithmetic unit (VAU), the scalar arithmetic unit (SAU), and the integer arithmetic unit (IAU). Additionally, every SHAVE core also incorporates a its own [[texture mapping unit]] (TMU), allowing for powerful bitmap transformations.
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| − | The '''integer arithmetic unit''' ('''IAU''') performs all arithmetic instructions that operate on 32-bit integer numbers and access the IRF. The '''scalar arithmetic unit''' ('''SAU''') is far more versatile and can perform all [[integer]] (8-32 bit) and [[floating point]] (HP/FP) operations. The '''vector arithmetic unit''' ('''VAU''') supports 128-bit vector operations of all the integer (8-32 bit) and floating point (HP/FP) types. Since those operations can be done at in the same cycle, it's possible to perform combination of the two in order to do various DSP-like operations such as matrix switching.
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| − | In addition to those units, there is also a '''compare-move unit''' ('''CMU''') which is used to generate [[predicates]]. This unit can do things such as three comparison operations per 16-bit/32-bit/8bit entry in the vector register file in parallel with the vector operations which can generate predicates for predicated execution. The CMU effectively interfaces with all the register files and is capable of moving data between them.
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| − | The '''branch and repeat unit''' ('''BRU''') is another execution unit with the ability to do continuous iterations with zero overhead. This applies to single or multiple VLIW words and can be used for things usch as parameterizable [[finite impulse response]] (FIR) filters, allowing for significant instruction fetch bandwidth reduction.
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| − | Both the CMU and the BRU can work in conjunction with the '''predicated execution unit''' ('''PEU''') and they work with the VAU all in the same cycle, meaning applications such as pixel decision making can be done incredibly fast in the same cycle.
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| − | === Memory Subsystem ===
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| − | [[File:shave v2 mem subsys.svg|right|300px]]
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| − | Each SHAVE core has two [[load-store units]], each is capable of doing a single 64-bit operation per cycle from the SRAM tile.
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| − | Each SHAVE core has a local 128 KiB slice of SRAM the LSU operates on [[Movidius]] calls the Connection MatriX (CMX) block. The cache is split between [[instruction cache|instruction]] and [[data cache|data]]. The exact amount is software configurable with a granularity of 8 KiB intervals. Each local cache tile is directly linked to two of its closest neighbors (presumably to the cores located to the west and to the east), allowing for zero-penalty accesses from those memory banks as well. For cache tiles located further on do have a slight latency penalty. Movidius noted that most of the software they've tested does almost all of its communication with its neighboring cores, allowing them to take advantage of this.
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| − | The entire chip also has a share 128 KiB of L2 cache and a integrated [[DDR2]] [[integrated memory controller|memory controller]] which is connected to an on-package stacked 8-64 MiB of [[SDRAM]].
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| | | | |
| | === Bandwidth === | | === Bandwidth === |
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| | :[[File:movidius shave v2.0 sparse data support.png|700px]] | | :[[File:movidius shave v2.0 sparse data support.png|700px]] |
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| − | == Inter-core communication ==
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| − | This architecture does not have support for hardware synchronization primitives, however it does have a light communication system.
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| − | Each of the SHAVE cores has a small arbitration messaging [[queue]] consisting of four entries of 64-bit words which is only accessibly (read-wise) from that core. Each SHAVE core can send a message to any other core. When this happens the message is pushed onto that core's queue. If that core's queue is full, the sender will stall. This allows for very efficient SHAVE-SHAVE synchronization and communication without using any shared memory techniques.
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| − | It's worth noting that the control/management [[LEON3]] [[SPARC]] core does not have access to this communication system.
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| | == Performance claims == | | == Performance claims == |
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| | == Package == | | == Package == |
| | [[File:myriad 1 bga.png|right|200px]] | | [[File:myriad 1 bga.png|right|200px]] |
| − | Movidius packaged those chips in an 8x8 mm [[BGA]] package with 225 [[solder ball|balls]]. The die is then bumped on top of a custom [[FR-4 substrate]]. The SDRAM is then [[wire bond|wire bond]] on top of the Myriad die. | + | Movidius packaged those chips in an 8x8 mm [[BGA]] package with 225 [[solder ball|balls]]. The die is then bumpped on top of a custom [[FR-4 substrate]]. The SDRAM is then [[wire bond|wire bond]] on top of the Myriad die. |
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| | :[[File:myriad package diagram.svg|600px]] | | :[[File:myriad package diagram.svg|600px]] |
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| − | :[[File:myriad 1 (shave v2.0) die shot.png|class=wikichip_ogimage|600px]] | + | :[[File:myriad 1 (shave v2.0) die shot.png|600px]] |
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| | :[[File:myriad 1 (shave v2.0) die shot (annotated).png|600px]] | | :[[File:myriad 1 (shave v2.0) die shot (annotated).png|600px]] |
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| − | == All SHAVE v2.0 Chips ==
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| − | <!-- NOTE:
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| − | This table is generated automatically from the data in the actual articles.
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| − | If a microprocessor is missing from the list, an appropriate article for it needs to be
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| − | created and tagged accordingly.
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| − |
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| − | Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
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| − | -->
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| − | {{comp table start}}
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| − | <table class="comptable sortable tc4">
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| − | {{comp table header|main|5:List of SHAVE v2.0-based Processors}}
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| − | {{comp table header|main|5:Main processor}}
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| − | {{comp table header|cols|Price|Launched|Cores|%Frequency}}
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| − | {{#ask: [[Category:microprocessor models by movidius]] [[microarchitecture::SHAVE v2.0]]
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| − | |?full page name
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| − | |?model number
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| − | |?release price
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| − | |?first launched
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| − | |?core count
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| − | |?base frequency#MHz
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| − | |format=template
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| − | |template=proc table 3
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| − | |userparam=6
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| − | |mainlabel=-
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| − | }}
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| − | {{comp table count|ask=[[Category:microprocessor models by movidius]] [[microarchitecture::SHAVE v2.0]]}}
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| − | </table>
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| − | {{comp table end}}
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| − |
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| − | == References ==
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| − | * Some information was obtained directly from Movidius
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| − | * HotChips 23 (HC23), 2011
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