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Difference between revisions of "mediatek/helio/mt6799"
< mediatek‎ | helio

Line 36: Line 36:
 
| isa                = ARMv8
 
| isa                = ARMv8
 
| microarch          = Cortex-A53
 
| microarch          = Cortex-A53
| microarch 2        = Cortex-A72
+
| microarch 2        = Cortex-A73
 
| platform            =  
 
| platform            =  
 
| chipset            =  
 
| chipset            =  
 
| core name          = Cortex-A53
 
| core name          = Cortex-A53
| core name 2        = Cortex-A72
+
| core name 2        = Cortex-A73
 
| core family        =  
 
| core family        =  
 
| core model          =  
 
| core model          =  
Line 91: Line 91:
 
}}
 
}}
 
'''Helio X30''' is a {{arch|64}} [[deca-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] and set to be launched in early [[2017]]. This SoC incorporates 3 independent clusters of cores (called "Tri-Cluster" by MediaTek) operating at varying degrees of performance designed for certain workloads (operating at 2 GHz, 2.2 GHz, and 2.8 GHz) and supports dual-channel LPDDR3-1866. This SoC also incorporates a {{imgtec|PowerVR GT7400}} [[IGP]] operating at 870 MHz. The chip has a modem supporting [[LTE]] User Equipment (UE) category 10.
 
'''Helio X30''' is a {{arch|64}} [[deca-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] and set to be launched in early [[2017]]. This SoC incorporates 3 independent clusters of cores (called "Tri-Cluster" by MediaTek) operating at varying degrees of performance designed for certain workloads (operating at 2 GHz, 2.2 GHz, and 2.8 GHz) and supports dual-channel LPDDR3-1866. This SoC also incorporates a {{imgtec|PowerVR GT7400}} [[IGP]] operating at 870 MHz. The chip has a modem supporting [[LTE]] User Equipment (UE) category 10.
 +
 +
== Architecture ==
 +
The Helio X30 is designed is composed of 3 individual clusters of CPU cores depending on the level of performance required by the active applications.
 +
 +
* Extreme Performance - 2x {{armh|Cortex-A73|l=arch}} @ 2.8 GHz
 +
* Performance/Power Balance - 4x {{armh|Cortex-A53|l=arch}} @ 2.2 GHz
 +
* Power Efficiency - 4x {{armh|Cortex-A53|l=arch}} @ 2 GHz
 +
 +
The three clusters are designed as a modified {{armh|big.LITTLE}} configuration.
 +
 +
== Cache ==
 +
{{main|arm holdings/microarchitectures/cortex-a53#Memory_Hierarchy|arm holdings/microarchitectures/cortex-a73#Memory_Hierarchy|l1=Cortex-A53 § Cache|l2=Cortex-A73 § Cache}}
 +
{{empty section}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=LPDDR3-1866
 +
|ecc=No
 +
|max mem=8 GiB
 +
|controllers=1
 +
|channels=2
 +
|max bandwidth=27.81 GiB/s
 +
|bandwidth schan=13.9 GiB/s
 +
|bandwidth dchan=27.81 GiB/s
 +
}}
 +
 +
== Expansions ==
 +
{{expansions
 +
|usb revision=2.0
 +
|usb revision 2=3.0
 +
|usb ports=8
 +
|uart=4
 +
|gp io=Yes
 +
}}
 +
 +
== Graphics ==
 +
{{integrated graphics
 +
| gpu                = PowerVR GT7400
 +
| device id          =
 +
| designer            = Imagination Technologies
 +
| execution units    =
 +
| max displays        =
 +
| max memory          =
 +
| frequency          = 870 MHz
 +
 +
| output dsi          = Yes
 +
 +
| max res dsi        = 2560x1600
 +
 +
| direct3d ver        = 11.2
 +
| opencl ver          = 1.2
 +
| opengl ver          = 3.1
 +
| opengl es ver      = 3.1
 +
| vulkan ver          = 1.0
 +
}}
 +
 +
== Wireless ==
 +
{{wireless links
 +
| wifi              = Yes
 +
| 80211ac          = Yes
 +
 +
| 2g                = Yes
 +
| csd              = Yes
 +
| gsm              = Yes
 +
| gprs              = Yes
 +
| edge              = Yes
 +
| cdmaone          =
 +
| is-95a            =
 +
| is-95b            =
 +
| 3g                = Yes
 +
| cdma2000          = Yes
 +
| cdma2000 1x      = Yes
 +
| cdma2000 1xev-do  = Yes
 +
| cdma2000 1x adv  =
 +
| umts              = Yes
 +
| wcdma            = 
 +
| td-scdma          = Yes
 +
| dc-hsdpa          = Yes
 +
| hsdpa            =
 +
| hsupa            = Yes
 +
| 4g                = Yes
 +
| lte a            = Yes
 +
| e-utran          = Yes
 +
| ue cat            = 10
 +
}}

Revision as of 02:26, 5 December 2016

Template:mpu Helio X30 is a 64-bit deca-core ARM LTE system on a chip designed by MediaTek and set to be launched in early 2017. This SoC incorporates 3 independent clusters of cores (called "Tri-Cluster" by MediaTek) operating at varying degrees of performance designed for certain workloads (operating at 2 GHz, 2.2 GHz, and 2.8 GHz) and supports dual-channel LPDDR3-1866. This SoC also incorporates a PowerVR GT7400 IGP operating at 870 MHz. The chip has a modem supporting LTE User Equipment (UE) category 10.

Architecture

The Helio X30 is designed is composed of 3 individual clusters of CPU cores depending on the level of performance required by the active applications.

The three clusters are designed as a modified big.LITTLE configuration.

Cache

Main articles: Cortex-A53 § Cache and Cortex-A73 § Cache
New text document.svg This section is empty; you can help add the missing info by editing this page.

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR3-1866
Supports ECCNo
Max Mem8 GiB
Controllers1
Channels2
Max Bandwidth27.81 GiB/s
28,477.44 MiB/s
29.861 GB/s
29,860.76 MB/s
0.0272 TiB/s
0.0299 TB/s
Bandwidth
Single 13.9 GiB/s
Double 27.81 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
USB
Revision2.0, 3.0
Ports8
UART

GP I/OYes


Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR GT7400
DesignerImagination Technologies
Frequency870 MHz
0.87 GHz
870,000 KHz
OutputDSI

Max Resolution
DSI2560x1600

Standards
Direct3D11.2
OpenGL3.1
OpenCL1.2
OpenGL ES3.1
Vulkan1.0

Wireless

Antu network-wireless-connected-100.svgWireless Communications
Wi-Fi
WiFi
802.11acYes
Cellular
2G
CSD Yes
GSM Yes
GPRS Yes
EDGE Yes
3G
UMTS
TD-SCDMAYes
DC-HSDPAYes
HSUPAYes
CDMA2000
1XYes
1xEV-DOYes
4G
LTE Advanced
E-UTRANYes
UE Cat10