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− | {{mediatek title|Helio P15 | + | {{mediatek title|Helio P15}} |
− | {{ | + | {{mpu |
− | |name=Helio P15 | + | | future = Yes |
− | |no image= | + | | name = MediaTek Helio P15 |
− | |designer=MediaTek | + | | no image = yes |
− | |designer 2=ARM Holdings | + | | image = |
− | |manufacturer=TSMC | + | | image size = |
− | |model number=P15 | + | | caption = |
− | |part number=MT6755T | + | | designer = MediaTek |
− | |market=Mobile | + | | designer 2 = ARM Holdings |
− | |market 2=Embedded | + | | manufacturer = TSMC |
− | |first announced=October 17, 2016 | + | | model number = Helio P15 |
− | |first launched= | + | | part number = MT6755T? |
− | |family=Helio | + | | part number 2 = MTK6755T? |
− | |series=Helio P | + | | market = Mobile |
− | |frequency=2,200 MHz | + | | market 2 = Embedded |
− | |frequency 2=1,200 MHz | + | | first announced = October 17, 2016 |
− | |bus type=AMBA 4 AXI | + | | first launched = |
− | | | + | | last order = |
− | |isa family=ARM | + | | last shipment = |
− | |microarch=Cortex-A53 | + | | release price = |
− | |core name=Cortex-A53 | + | |
− | |process=28 nm | + | | family = Helio |
− | |technology=CMOS | + | | series = Helio P |
− | |word size=64 bit | + | | locked = |
− | |core count=8 | + | | frequency = 2,200 MHz |
− | |thread count=8 | + | | frequency 2 = 1,200 MHz |
− | |max cpus=1 | + | | bus type = AMBA 4 AXI |
− | |max memory=4 GiB | + | | bus speed = |
− | |v core=1 V | + | | bus rate = |
− | |v io=1.8 V | + | | bus links = |
− | |v io 2=2.8 V | + | | clock multiplier = |
− | |v io 3=3.3 V | + | |
− | |temp min=-20 °C | + | | isa family = ARM |
− | |temp max=80 °C | + | | isa = ARMv8 |
− | |tjunc max=125 °C | + | | microarch = Cortex-A53 |
− | |tstorage min=0 °C | + | | platform = |
− | |tstorage max=125 °C | + | | chipset = |
+ | | core name = Cortex-A53 | ||
+ | | core family = | ||
+ | | core model = | ||
+ | | core stepping = | ||
+ | | process = 28 nm | ||
+ | | transistors = | ||
+ | | technology = CMOS | ||
+ | | die area = <!-- XX mm² --> | ||
+ | | die width = | ||
+ | | die length = | ||
+ | | word size = 64 bit | ||
+ | | core count = 8 | ||
+ | | thread count = 8 | ||
+ | | max cpus = 1 | ||
+ | | max memory = 4 GiB | ||
+ | |||
+ | | electrical = Yes | ||
+ | | power = | ||
+ | | v core = 1 V | ||
+ | | v core tolerance = | ||
+ | | v io = 1.8 V | ||
+ | | v io 2 = 2.8 V | ||
+ | | v io 3 = 3.3 V | ||
+ | | sdp = | ||
+ | | tdp = | ||
+ | | tdp typical = | ||
+ | | ctdp down = | ||
+ | | ctdp down frequency = | ||
+ | | ctdp up = | ||
+ | | ctdp up frequency = | ||
+ | | temp min = -20 °C | ||
+ | | temp max = 80 °C | ||
+ | | tjunc min = | ||
+ | | tjunc max = 125 °C | ||
+ | | tcase min = | ||
+ | | tcase max = | ||
+ | | tstorage min = 0 °C | ||
+ | | tstorage max = 125 °C | ||
+ | | tambient min = | ||
+ | | tambient max = | ||
+ | |||
+ | | packaging = | ||
+ | | package 0 = | ||
+ | | package 0 type = | ||
+ | | package 0 pins = | ||
+ | | package 0 pitch = | ||
+ | | package 0 width = | ||
+ | | package 0 length = | ||
+ | | package 0 height = | ||
}} | }} | ||
− | '''Helio P15''' ('''MT6755T''') is a {{arch|64}} [[octa-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] and introduced in early-[[2016]]. This SoC, which incorporates eight {{armh|Cortex-A53|l=arch}} cores and is manufactured on [[TSMC]]'s [[28 nm process]], operates at up to 2.2 GHz and supports | + | '''Helio P15''' ('''MT6755T'''?) is a {{arch|64}} [[octa-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] and introduced in early-[[2016]]. This SoC, which incorporates eight {{armh|Cortex-A53|l=arch}} cores and is manufactured on [[TSMC]]'s [[28 nm process]], operates at up to 2.2 GHz and supports single-channel LPDDR3-933. This chip incorporates the {{imgtec|Mali-T880}} [[IGP]] operating at 800 MHz. This SoC has a modem supporting [[LTE]] User Equipment (UE) category 6. |
This processor is made of two independent clusters of {{armh|Cortex-A53|l=arch}} with four cores each linked together via a {{armh|CCI-400}}. The two clusters have a maximum operating frequency of 2.2 GHz and 1.2 GHz respectively. | This processor is made of two independent clusters of {{armh|Cortex-A53|l=arch}} with four cores each linked together via a {{armh|CCI-400}}. The two clusters have a maximum operating frequency of 2.2 GHz and 1.2 GHz respectively. | ||
The Helio P15 is identical to the {{\\|Helio P10}} with higher clock speeds for both the GPU and CPU. | The Helio P15 is identical to the {{\\|Helio P10}} with higher clock speeds for both the GPU and CPU. | ||
− | |||
== Cache == | == Cache == | ||
{{main|arm holdings/microarchitectures/cortex-a53#Memory_Hierarchy|l1=Cortex-A53 § Cache}} | {{main|arm holdings/microarchitectures/cortex-a53#Memory_Hierarchy|l1=Cortex-A53 § Cache}} | ||
Line 61: | Line 109: | ||
== Memory controller == | == Memory controller == | ||
{{memory controller | {{memory controller | ||
− | |type=LPDDR3- | + | |type=LPDDR3-933 |
|ecc=No | |ecc=No | ||
|max mem=4 GiB | |max mem=4 GiB | ||
|controllers=1 | |controllers=1 | ||
|channels=1 | |channels=1 | ||
− | |||
|max bandwidth=6.95 GiB/s | |max bandwidth=6.95 GiB/s | ||
|bandwidth schan=6.95 GiB/s | |bandwidth schan=6.95 GiB/s | ||
Line 160: | Line 207: | ||
== Utilizing devices == | == Utilizing devices == | ||
− | * [[used by:: | + | {{empty section}} |
+ | <!-- | ||
+ | * [[used by::xxxxxxxxxxxxxxx]] | ||
+ | * [[used by::xxxxxxxxxxxxxxx]] | ||
+ | --> | ||
{{expand list}} | {{expand list}} |
Facts about "Helio P15 (MT6755T) - MediaTek"
base frequency | 2,200 MHz (2.2 GHz, 2,200,000 kHz) + and 1,200 MHz (1.2 GHz, 1,200,000 kHz) + |
bus type | AMBA 4 AXI + |
core count | 8 + |
core name | Cortex-A53 + |
core voltage | 1 V (10 dV, 100 cV, 1,000 mV) + |
designer | MediaTek + and ARM Holdings + |
family | Helio + |
first announced | October 17, 2016 + |
first launched | April 2017 + |
full page name | mediatek/helio/mt6755t + |
has 2g support | true + |
has 3g support | true + |
has 4g support | true + |
has csd support | true + |
has dc-hsdpa support | true + |
has e-utran support | true + |
has ecc memory support | false + |
has edge support | true + |
has gprs support | true + |
has gsm support | true + |
has hsupa support | true + |
has lte advanced support | true + |
has td-scdma support | true + |
has umts support | true + |
instance of | microprocessor + |
integrated gpu | Mali-T860 + |
integrated gpu base frequency | 800 MHz (0.8 GHz, 800,000 KHz) + |
integrated gpu designer | ARM Holdings + |
integrated gpu execution units | 2 + |
io voltage | 1.8 V (18 dV, 180 cV, 1,800 mV) +, 2.8 V (28 dV, 280 cV, 2,800 mV) + and 3.3 V (33 dV, 330 cV, 3,300 mV) + |
isa | ARMv8 + |
isa family | ARM + |
l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1d$ description | 4-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 2-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
ldate | April 2017 + |
manufacturer | TSMC + |
market segment | Mobile + and Embedded + |
max cpu count | 1 + |
max junction temperature | 398.15 K (125 °C, 257 °F, 716.67 °R) + |
max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + |
max memory bandwidth | 6.95 GiB/s (7,116.8 MiB/s, 7.463 GB/s, 7,462.506 MB/s, 0.00679 TiB/s, 0.00746 TB/s) + |
max memory channels | 1 + |
max operating temperature | 80 °C + |
max storage temperature | 398.15 K (125 °C, 257 °F, 716.67 °R) + |
microarchitecture | Cortex-A53 + |
min operating temperature | -20 °C + |
min storage temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
model number | P15 + |
name | Helio P15 + |
part number | MT6755T + |
process | 28 nm (0.028 μm, 2.8e-5 mm) + |
series | Helio P + |
smp max ways | 1 + |
supported memory type | LPDDR3-1866 + |
technology | CMOS + |
thread count | 8 + |
used by | Motorola Moto M + |
user equipment category | 6 + |
word size | 64 bit (8 octets, 16 nibbles) + |