Semiconductor & Computer Engineering
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Difference between revisions of "intrinsity/fastmath/fastmath-lp"
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| + | {{mpu | ||
| + | | name = FastMATH-LP | ||
| + | | no image = | ||
| + | | image = | ||
| + | | image size = | ||
| + | | caption = | ||
| + | | designer = Intrinsity | ||
| + | | manufacturer = TSMC | ||
| + | | model number = | ||
| + | | part number = | ||
| + | | part number 1 = | ||
| + | | market = Embedded | ||
| + | | first announced = 2002 | ||
| + | | first launched = 2003 | ||
| + | | last order = | ||
| + | | last shipment = | ||
| + | |||
| + | | family = FastMATH | ||
| + | | series = | ||
| + | | locked = | ||
| + | | frequency = 1,000 MHz | ||
| + | | bus type = RapidIO | ||
| + | | bus speed = 500 MHz | ||
| + | | bus rate = 4 GT/s | ||
| + | | clock multiplier = | ||
| + | |||
| + | | microarch = FashMATH | ||
| + | | platform = | ||
| + | | chipset = | ||
| + | | core name = | ||
| + | | core family = | ||
| + | | core model = | ||
| + | | core stepping = | ||
| + | | process = 130 nm | ||
| + | | transistors = | ||
| + | | technology = Dynamic CMOS | ||
| + | | die size = | ||
| + | | word size = 32 bit | ||
| + | | core count = 1 | ||
| + | | thread count = 1 | ||
| + | | max cpus = | ||
| + | | max memory = | ||
| + | | max memory addr = | ||
| + | |||
| + | | electrical = Yes | ||
| + | | power = 6 W | ||
| + | | v core = 0.85 V | ||
| + | | v core tolerance = | ||
| + | | sdp = | ||
| + | | tdp = | ||
| + | | ctdp down = | ||
| + | | ctdp down frequency = | ||
| + | | ctdp up = | ||
| + | | ctdp up frequency = | ||
| + | | temp min = | ||
| + | | temp max = | ||
| + | | tjunc min = | ||
| + | | tjunc max = | ||
| + | | tcase min = | ||
| + | | tcase max = | ||
| + | | tstorage min = | ||
| + | | tstorage max = | ||
| + | |||
| + | | packaging = Yes | ||
| + | | package 0 = CBGA-670 | ||
| + | | package 0 type = CBGA | ||
| + | | package 0 pins = 670 | ||
| + | | package 0 pitch = | ||
| + | | package 0 width = | ||
| + | | package 0 length = | ||
| + | | package 0 height = | ||
| + | | socket 0 = | ||
| + | | socket 0 type = | ||
| + | }} | ||
The '''FastMATH-LP''' was a microprocessor developed by [[Intrinsity]] operating at 1 GHz. The processor incorporates a high-performance [[MIPS]] CPU along with a powerful matrix and vector math unit. This mode was a low-power (LP) version of the normal FastMATH processor, operating at half the speed. | The '''FastMATH-LP''' was a microprocessor developed by [[Intrinsity]] operating at 1 GHz. The processor incorporates a high-performance [[MIPS]] CPU along with a powerful matrix and vector math unit. This mode was a low-power (LP) version of the normal FastMATH processor, operating at half the speed. | ||
Revision as of 16:49, 3 July 2016
Template:mpu The FastMATH-LP was a microprocessor developed by Intrinsity operating at 1 GHz. The processor incorporates a high-performance MIPS CPU along with a powerful matrix and vector math unit. This mode was a low-power (LP) version of the normal FastMATH processor, operating at half the speed.
