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==== W-3200-Series (Cascade Lake) ==== | ==== W-3200-Series (Cascade Lake) ==== | ||
{{main|intel/microarchitectures/cascade lake|l1=Cascade Lake Microarchitecture}} | {{main|intel/microarchitectures/cascade lake|l1=Cascade Lake Microarchitecture}} | ||
− | In early 2019 Intel launched their W-3200 series processors based on the {{intel|Cascade Lake|l=arch}} microarchitecture. Those processors are fabricated on an enhanced [[14 nm process]] which allows for higher clock speeds and introduced a {{intel|Cascade Lake#Key changes from Skylake|l=arch|number of}} hardware changes against the various [[speculative execution]] [[side channel analysis|vulnerabilities]]. Those processors also introduced new {{x86|AVX-512 VNNI|new instructions}} for the [[acceleration]] of machine learning (inference) | + | In early 2019 Intel launched their W-3200 series processors based on the {{intel|Cascade Lake|l=arch}} microarchitecture. Those processors are fabricated on an enhanced [[14 nm process]] which allows for higher clock speeds and introduced a {{intel|Cascade Lake#Key changes from Skylake|l=arch|number of}} hardware changes against the various [[speculative execution]] [[side channel analysis|vulnerabilities]]. Those processors also introduced new {{x86|AVX-512 VNNI|new instructions}} for the [[acceleration]] of machine learning (inference) and {{intel|Turbo Boost Max}}. All models have 48 [[PCIe]] lanes and have all the following features in common: |
* '''Proc:''' [[14 nm process]] | * '''Proc:''' [[14 nm process]] | ||
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* '''Mem:''' 1 TiB of hexa-channel DDR4-2933 ECC Memory | * '''Mem:''' 1 TiB of hexa-channel DDR4-2933 ECC Memory | ||
** "''M''" models have 2 TiB extended memory support | ** "''M''" models have 2 TiB extended memory support | ||
− | * '''I/O:''' | + | * '''I/O:''' 48 [[PCIe]] 3.0 Lanes |
* '''TDP:''' 160 W, 180 W, 205 W | * '''TDP:''' 160 W, 180 W, 205 W | ||
* '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, {{x86|AVX-512}}-{{x86|AVX512F|F}}/{{x86|AVX512CD|CD}}/{{x86|AVX512BW|BW}}/{{x86|AVX512DQ|DQ}}/{{x86|AVX512VL|VL}}/{{x86|AVX512VNNI|VNNI}} with 2 FMA units) | * '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, {{x86|AVX-512}}-{{x86|AVX512F|F}}/{{x86|AVX512CD|CD}}/{{x86|AVX512BW|BW}}/{{x86|AVX512DQ|DQ}}/{{x86|AVX512VL|VL}}/{{x86|AVX512VNNI|VNNI}} with 2 FMA units) |
Facts about "Xeon W - Intel"
designer | Intel + |
first announced | August 29, 2017 + |
first launched | August 29, 2017 + |
full page name | intel/xeon w + |
instance of | microprocessor family + |
instruction set architecture | x86-64 + |
main designer | Intel + |
manufacturer | Intel + |
microarchitecture | Skylake + and Cascade Lake + |
name | Xeon W + |
package | FCLGA-2066 or FCLGA3647 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
socket | Socket R4 or Socket P + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |