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| isa = x86-64 | | isa = x86-64 | ||
| microarch = Skylake | | microarch = Skylake | ||
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| word = 64 bit | | word = 64 bit | ||
| proc = 14 nm | | proc = 14 nm | ||
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| clock min = 2.3 GHz | | clock min = 2.3 GHz | ||
| clock max = 4.0 GHz | | clock max = 4.0 GHz | ||
− | | package = FCLGA-2066 | + | | package = FCLGA-2066 |
− | | socket = Socket R4 | + | | socket = Socket R4 |
| succession = Yes | | succession = Yes | ||
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== Overview == | == Overview == | ||
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The Xeon W family targets business and enterprise-class performance workstations, situated below the scalable Xeon family and above the {{intel|Xeon E3}}. Compared to the {{intel|Xeon E3}}, Xeon W come with more cores, more [[PCIe]] lanes, [[ECC]] memory, generally almost all available technologies offered by the chip, volume management and various RAS features. | The Xeon W family targets business and enterprise-class performance workstations, situated below the scalable Xeon family and above the {{intel|Xeon E3}}. Compared to the {{intel|Xeon E3}}, Xeon W come with more cores, more [[PCIe]] lanes, [[ECC]] memory, generally almost all available technologies offered by the chip, volume management and various RAS features. | ||
− | + | [[File:intel xeon w intro.jpg|left|100px]] | |
− | + | Introduced in August 2017, the Xeon W family is [[Intel]]'s family of workstation-class processors. Prior to their introduction, this segment was served by {{intel|Xeon E5}} family 1600-series. Prior to {{intel|Skylake (server)|Skylake|l=arch}}, the server segment and high-HEDT as well as workstations shared the same socket. With Skylake, the server segment diverged with the workstations and [[HEDT]] parts having their own [[socket]]. The Xeon W family and the HEDT {{intel|Core i7}}/{{intel|Core i9}} parts share the same socket. | |
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== Members == | == Members == | ||
− | + | === W-2100-Series (Skylake) === | |
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{{main|intel/microarchitectures/skylake (server)|l1=Skylake (server) Microarchitecture}} | {{main|intel/microarchitectures/skylake (server)|l1=Skylake (server) Microarchitecture}} | ||
Skylake-based Xeon W processors come with all the features enabled and only [[core count]] and {{intel|frequency behavior|frequency}} being the differentiating feature, with the exception of the two low-end models. For the most part, all models come with {{x86|AVX-512}} along with two full execution units, similar to the high-end {{intel|Skylake SP|l=core}} models. All models have 48 [[PCIe]] lanes and have all the following features in common: | Skylake-based Xeon W processors come with all the features enabled and only [[core count]] and {{intel|frequency behavior|frequency}} being the differentiating feature, with the exception of the two low-end models. For the most part, all models come with {{x86|AVX-512}} along with two full execution units, similar to the high-end {{intel|Skylake SP|l=core}} models. All models have 48 [[PCIe]] lanes and have all the following features in common: | ||
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* '''I/O:''' 48 [[PCIe]] 3.0 Lanes | * '''I/O:''' 48 [[PCIe]] 3.0 Lanes | ||
* '''TDP:''' 120 W / 140 W | * '''TDP:''' 120 W / 140 W | ||
− | * '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, | + | * '''ISA:''' Everything up to {{x86|AVX-512}} (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX512F, AVX512CD, AVX512BW, AVX512DQ, AVX512VL) |
* '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}/{{intel|EPT}}, {{intel|VT-d}}, {{intel|TBT 2.0}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|SpeedStep}}, {{intel|Identity Protection}}, {{intel|Secure Key}}, {{intel|MPX}}, {{intel|OS Guard}}, and {{intel|Volume Management Device}} (VMD). | * '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}/{{intel|EPT}}, {{intel|VT-d}}, {{intel|TBT 2.0}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|SpeedStep}}, {{intel|Identity Protection}}, {{intel|Secure Key}}, {{intel|MPX}}, {{intel|OS Guard}}, and {{intel|Volume Management Device}} (VMD). | ||
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{{comp table start}} | {{comp table start}} | ||
<table class="comptable sortable tc4 tc5 tc11"> | <table class="comptable sortable tc4 tc5 tc11"> | ||
− | {{comp table header|main| | + | {{comp table header|main|10:List of Skylake W-based Processors}} |
− | {{comp table header|cols|Launched|Price|Cores|Threads|TDP|L2|L3|%Frequency|%Turbo| | + | {{comp table header|cols|Launched|Price|Cores|Threads|TDP|L2|L3|%Frequency|%Turbo|AVX-512 Units}} |
{{#ask: [[Category:microprocessor models by intel]] [[core name::Skylake W]] | {{#ask: [[Category:microprocessor models by intel]] [[core name::Skylake W]] | ||
|?full page name | |?full page name | ||
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|?base frequency#GHz | |?base frequency#GHz | ||
|?turbo frequency (1 core)#GHz | |?turbo frequency (1 core)#GHz | ||
− | |? | + | |?number of avx-512 execution units |
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|format=template | |format=template | ||
|template=proc table 3 | |template=proc table 3 | ||
− | |userparam= | + | |userparam=12 |
|sort=model number | |sort=model number | ||
|mainlabel=- | |mainlabel=- | ||
}} | }} | ||
{{comp table count|ask=[[Category:microprocessor models by intel]] [[core name::Skylake W]]}} | {{comp table count|ask=[[Category:microprocessor models by intel]] [[core name::Skylake W]]}} | ||
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</table> | </table> | ||
{{comp table end}} | {{comp table end}} |
Facts about "Xeon W - Intel"
designer | Intel + |
first announced | August 29, 2017 + |
first launched | August 29, 2017 + |
full page name | intel/xeon w + |
instance of | microprocessor family + |
instruction set architecture | x86-64 + |
main designer | Intel + |
manufacturer | Intel + |
microarchitecture | Skylake + and Cascade Lake + |
name | Xeon W + |
package | FCLGA-2066 or FCLGA3647 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
socket | Socket R4 or Socket P + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |