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{{intel title|Xeon Silver 4214R}}
 
{{intel title|Xeon Silver 4214R}}
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{{chip
+
{{chip}}
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|name=Xeon Silver 4214R
 
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|image=cascade lake sp (front).png
 
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|designer=Intel
 
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|manufacturer=Intel
 
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|model number=4214R
 
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|market=Server
 
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|first announced=February 24, 2020
 
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|first launched=February 24, 2020
 
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|release price (tray)=$705.00
 
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|release price (box)=$694.00
 
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|family=Xeon Silver
 
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|series=4200
 
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|frequency=2,400 MHz
 
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|turbo frequency1=3,500 MHz
 
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|bus type=DMI 3.0
 
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|bus links=4
 
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|bus rate=8 GT/s
 
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|clock multiplier=24
 
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|isa=x86-64
 
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|isa family=x86
 
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|microarch=Cascade Lake
 
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|platform=Purley
 
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|chipset=Lewisburg
 
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|core name=Cascade Lake R
 
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|core family=6
 
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|process=14 nm
 
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|technology=CMOS
 
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|word size=64 bit
 
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|core count=12
 
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|thread count=24
 
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|max memory=1 TiB
 
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|max cpus=2
 
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|smp interconnect=UPI
 
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|smp interconnect links=2
 
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|smp interconnect rate=9.6 GT/s
 
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|tdp=100 W
 
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|tcase min=0 °C
 
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|tcase max=79 °C
 
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|package name 1=intel,fclga_3647
 
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|predecessor=Xeon Silver 4214
 
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|predecessor link=intel/xeon silver/4214
 
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}}
 
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'''Xeon Silver 4214R''' is a {{arch|64}} [[deca-core]] [[x86]] mid-range performance server microprocessor introduced by [[Intel]] in early [[2020]]. The Silver 4214R is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports dual-way multiprocessing, sports one {{x86|AVX-512}} [[FMA]] units as well as two {{intel|Ultra Path Interconnect|UPI}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2400 memory, operates at 2.4 GHz with a TDP of 100 W and features a {{intel|turbo boost}} frequency of up to 3.5 GHz.
 
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== Cache ==
 
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{{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}}
 
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{{cache size
 
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|l1 cache=768 KiB
 
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|l1i cache=384 KiB
 
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|l1i break=12x32 KiB
 
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|l1i desc=8-way set associative
 
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|l1d cache=384 KiB
 
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|l1d break=12x32 KiB
 
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|l1d desc=8-way set associative
 
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|l1d policy=write-back
 
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|l2 cache=12 MiB
 
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|l2 break=12x1 MiB
 
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|l2 desc=16-way set associative
 
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|l2 policy=write-back
 
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|l3 cache=16.5 MiB
 
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|l3 break=12x1.375 MiB
 
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|l3 desc=11-way set associative
 
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|l3 policy=write-back
 
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}}
 
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== Memory controller ==
 
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{{memory controller
 
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|type=DDR4-2400
 
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|ecc=Yes
 
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|max mem=1 TiB
 
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|controllers=2
 
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|channels=6
 
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|max bandwidth=107.3 GiB/s
 
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|bandwidth schan=17.88 GiB/s
 
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|bandwidth dchan=35.76 GiB/s
 
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|bandwidth qchan=71.53 GiB/s
 
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|bandwidth hchan=107.3 GiB/s
 
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}}
 
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== Expansions ==
 
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{{expansions main
 
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|
 
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{{expansions entry
 
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|type=PCIe
 
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|pcie revision=3.0
 
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|pcie lanes=48
 
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|pcie config=1x16
 
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|pcie config 2=x8
 
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|pcie config 3=x4
 
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}}
 
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}}
 
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== Features ==
 
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{{x86 features
 
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|real=Yes
 
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|protected=Yes
 
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|smm=Yes
 
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|fpu=Yes
 
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|x8616=Yes
 
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|x8632=Yes
 
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|x8664=Yes
 
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|nx=Yes
 
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|mmx=Yes
 
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|emmx=Yes
 
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|sse=Yes
 
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|sse2=Yes
 
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|sse3=Yes
 
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|ssse3=Yes
 
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|sse41=Yes
 
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|sse42=Yes
 
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|sse4a=No
 
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|avx=Yes
 
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|avx2=Yes
 
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|avx512f=Yes
 
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|avx512cd=Yes
 
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|avx512er=No
 
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|avx512pf=No
 
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|avx512bw=Yes
 
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|avx512dq=Yes
 
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|avx512vl=Yes
 
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|avx512ifma=No
 
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|avx512vbmi=No
 
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|avx5124fmaps=No
 
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|avx512vnni=Yes
 
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|avx5124vnniw=No
 
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|avx512vpopcntdq=No
 
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|abm=Yes
 
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|tbm=No
 
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|bmi1=Yes
 
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|bmi2=Yes
 
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|fma3=Yes
 
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|fma4=No
 
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|aes=Yes
 
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|rdrand=Yes
 
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|sha=No
 
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|xop=No
 
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|adx=Yes
 
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|clmul=Yes
 
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|f16c=Yes
 
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|bfloat16=No
 
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|tbt1=No
 
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|tbt2=Yes
 
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|tbmt3=No
 
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|bpt=No
 
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|eist=Yes
 
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|sst=Yes
 
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|flex=No
 
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|fastmem=No
 
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|ivmd=Yes
 
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|intelnodecontroller=No
 
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|intelnode=Yes
 
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|kpt=Yes
 
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|ptt=Yes
 
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|intelrunsure=No
 
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|mbe=Yes
 
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|isrt=No
 
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|sba=No
 
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|mwt=No
 
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|sipp=No
 
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|att=No
 
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|ipt=No
 
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|tsx=Yes
 
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|txt=Yes
 
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|ht=Yes
 
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|vpro=Yes
 
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|vtx=Yes
 
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|vtd=Yes
 
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|ept=Yes
 
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|mpx=No
 
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|sgx=No
 
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|securekey=No
 
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|osguard=No
 
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|intqat=No
 
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|dlboost=Yes
 
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|3dnow=No
 
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|e3dnow=No
 
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|smartmp=No
 
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|powernow=No
 
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|amdvi=No
 
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|amdv=No
 
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|amdsme=No
 
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|amdtsme=No
 
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|amdsev=No
 
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|rvi=No
 
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|smt=No
 
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|sensemi=No
 
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|xfr=No
 
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|xfr2=No
 
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|mxfr=No
 
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|amdpb=No
 
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|amdpb2=No
 
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|amdpbod=No
 
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}}
 
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== Frequencies ==
 
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{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 
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{{frequency table
 
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|freq_base=2,400MHz
 
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|freq_1=3,500MHz
 
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|freq_2=3,500MHz
 
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|freq_3=3,300MHz
 
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|freq_4=3,300MHz
 
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|freq_5=3,200MHz
 
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|freq_6=3,200MHz
 
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|freq_7=3,200MHz
 
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|freq_8=3,200MHz
 
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|freq_9=3,000MHz
 
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|freq_10=3,000MHz
 
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|freq_11=3,000MHz
 
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|freq_12=3,000MHz
 
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|freq_avx2_base=2,100MHz
 
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|freq_avx2_1=3,100MHz
 
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|freq_avx2_2=3,100MHz
 
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|freq_avx2_3=2,900MHz
 
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|freq_avx2_4=2,900MHz
 
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|freq_avx2_5=2,800MHz
 
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|freq_avx2_6=2,800MHz
 
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|freq_avx2_7=2,800MHz
 
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|freq_avx2_8=2,800MHz
 
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|freq_avx2_9=2,700MHz
 
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|freq_avx2_10=2,700MHz
 
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|freq_avx2_11=2,700MHz
 
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|freq_avx2_12=2,700MHz
 
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|freq_avx512_base=1,600MHz
 
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|freq_avx512_1=2,300MHz
 
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|freq_avx512_2=2,300MHz
 
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|freq_avx512_3=2,100MHz
 
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|freq_avx512_4=2,100MHz
 
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|freq_avx512_5=2,000MHz
 
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|freq_avx512_6=2,000MHz
 
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|freq_avx512_7=2,000MHz
 
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|freq_avx512_8=2,000MHz
 
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|freq_avx512_9=1,900MHz
 
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|freq_avx512_10=1,900MHz
 
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|freq_avx512_11=1,900MHz
 
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|freq_avx512_12=1,900MHz
 
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}}
 

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Retrieved from "https://en.wikichip.org/wiki/intel/xeon_silver/4214r"
Facts about "Xeon Silver 4214R - Intel"
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Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon Silver 4214R - Intel#pcie +
base frequency2,400 MHz (2.4 GHz, 2,400,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typeDMI 3.0 +
chipsetLewisburg +
clock multiplier24 +
core count12 +
core family6 +
core nameCascade Lake R +
designerIntel +
familyXeon Silver +
first announcedFebruary 24, 2020 +
first launchedFebruary 24, 2020 +
full page nameintel/xeon silver/4214r +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Encryption Standard Instruction Set Extension +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Deep Learning Boost +, Enhanced SpeedStep Technology +, Extended Page Tables +, Hyper-Threading Technology +, Intel VT-d +, Intel VT-x +, Intel vPro Technology +, Speed Shift Technology +, Transactional Synchronization Extensions +, Trusted Execution Technology + and Turbo Boost Technology 2.0 +
has intel deep learning boosttrue +
has intel enhanced speedstep technologytrue +
has intel speed shift technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size768 KiB (786,432 B, 0.75 MiB) +
l1d$ description8-way set associative +
l1d$ size384 KiB (393,216 B, 0.375 MiB) +
l1i$ description8-way set associative +
l1i$ size384 KiB (393,216 B, 0.375 MiB) +
l2$ description16-way set associative +
l2$ size12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) +
l3$ description11-way set associative +
l3$ size16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) +
ldateFebruary 24, 2020 +
main imageFile:cascade lake sp (front).png +
manufacturerIntel +
market segmentServer +
max case temperature352.15 K (79 °C, 174.2 °F, 633.87 °R) +
max cpu count2 +
max memory1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
max memory bandwidth107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) +
max memory channels6 +
microarchitectureCascade Lake +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model number4214R +
nameXeon Silver 4214R +
packageFCLGA-3647 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 705.00 (€ 634.50, £ 571.05, ¥ 72,847.65) + and $ 694.00 (€ 624.60, £ 562.14, ¥ 71,711.02) +
release price (box)$ 694.00 (€ 624.60, £ 562.14, ¥ 71,711.02) +
release price (tray)$ 705.00 (€ 634.50, £ 571.05, ¥ 72,847.65) +
series4200 +
smp interconnectUPI +
smp interconnect links2 +
smp interconnect rate9.6 GT/s +
smp max ways2 +
socketLGA-3647 + and Socket P +
supported memory typeDDR4-2400 +
tdp100 W (100,000 mW, 0.134 hp, 0.1 kW) +
technologyCMOS +
thread count24 +
turbo frequency (1 core)3,500 MHz (3.5 GHz, 3,500,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +