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{{intel title|Xeon Platinum 8164}} | {{intel title|Xeon Platinum 8164}} | ||
− | {{ | + | {{mpu |
− | |name=Xeon Platinum 8164 | + | | future = Yes |
− | |image= | + | | name = Xeon Platinum 8164 |
− | |designer=Intel | + | | no image = Yes |
− | |manufacturer=Intel | + | | image = |
− | |model number=8164 | + | | image size = |
− | |part number= | + | | caption = |
− | |part number 2= | + | | designer = Intel |
− | |s-spec=SR3BB | + | | manufacturer = Intel |
− | |s-spec | + | | model number = 8164 |
− | |market=Server | + | | part number = CD8067303408800 |
− | |first announced=April 25, 2017 | + | | part number 1 = |
− | |first launched= | + | | part number 2 = |
− | |release price= | + | | s-spec = SR3BB |
− | |family=Xeon Platinum | + | | s-spec 2 = |
− | |series= | + | | market = Server |
− | |frequency=2 | + | | first announced = April 25, 2017 |
− | |turbo frequency1=3 | + | | first launched = |
− | | | + | | last order = |
− | |clock multiplier=20 | + | | last shipment = |
− | |cpuid= | + | | release price = |
− | |isa=x86-64 | + | |
− | |isa | + | | family = Xeon Platinum |
− | |microarch=Skylake | + | | series = 8100 |
− | |platform=Purley | + | | locked = Yes |
− | |chipset=Lewisburg | + | | frequency = 2.0 GHz |
− | |core name=Skylake SP | + | | turbo frequency = |
− | |core family= | + | | turbo frequency1 = |
− | |core stepping=H0 | + | | turbo frequency2 = |
− | |process=14 nm | + | | turbo frequency3 = |
− | |technology=CMOS | + | | turbo frequency4 = |
− | |word size=64 bit | + | | turbo frequency5 = |
− | |core count=26 | + | | turbo frequency6 = |
− | |thread count=52 | + | | turbo frequency7 = |
− | |max memory= | + | | turbo frequency8 = |
− | |max | + | | bus type = DMI 3.0 |
− | | | + | | bus speed = |
− | | | + | | bus rate = 8 GT/s |
− | | | + | | bus links = 4 |
− | | | + | | clock multiplier = 20 |
− | |tcase min= | + | | cpuid = |
− | |tcase max= | + | | cpuid 2 = |
− | | | + | |
− | | | + | | isa family = x86-64 |
− | |package | + | | isa = x86 |
+ | | microarch = Skylake | ||
+ | | platform = Purley | ||
+ | | chipset = Lewisburg | ||
+ | | core name = Skylake SP | ||
+ | | core family = | ||
+ | | core model = | ||
+ | | core stepping = H0 | ||
+ | | process = 14 nm | ||
+ | | transistors = | ||
+ | | technology = CMOS | ||
+ | | die area = <!-- XX mm² --> | ||
+ | | die width = | ||
+ | | die length = | ||
+ | | word size = 64 bit | ||
+ | | core count = 26 | ||
+ | | thread count = 52 | ||
+ | | max cpus = 2 | ||
+ | | max memory = | ||
+ | |||
+ | | electrical = | ||
+ | | power = | ||
+ | | average power = | ||
+ | | idle power = | ||
+ | | v core = | ||
+ | | v core tolerance = <!-- OR ... --> | ||
+ | | v core min = | ||
+ | | v core max = | ||
+ | | v io = | ||
+ | | v io tolerance = | ||
+ | | v io 2 = <!-- OR ... --> | ||
+ | | v io 3 = | ||
+ | | sdp = | ||
+ | | tdp = | ||
+ | | tdp typical = | ||
+ | | ctdp down = | ||
+ | | ctdp down frequency = | ||
+ | | ctdp up = | ||
+ | | ctdp up frequency = | ||
+ | | temp min = <!-- use TJ/TC whenever possible instead --> | ||
+ | | temp max = | ||
+ | | tjunc min = <!-- .. °C --> | ||
+ | | tjunc max = | ||
+ | | tcase min = | ||
+ | | tcase max = | ||
+ | | tstorage min = | ||
+ | | tstorage max = | ||
+ | | tambient min = | ||
+ | | tambient max = | ||
+ | |||
+ | | package module 1 = | ||
+ | | package module 2 = | ||
+ | <!-------- USE ONLY IF MUST, OTHERWISE TRY TO USE MODULE ABOVE --------------> | ||
+ | | packaging = Yes | ||
+ | | package 0 = FCLGA-3647 | ||
+ | | package 0 type = LGA | ||
+ | | package 0 pins = 3647 | ||
+ | | package 0 pitch = | ||
+ | | package 0 width = | ||
+ | | package 0 length = | ||
+ | | package 0 height = | ||
+ | | socket 0 = LGA-3647 | ||
+ | | socket 0 type = LGA | ||
}} | }} | ||
− | '''Xeon Platinum 8164''' is a {{arch|64}} [[ | + | '''Xeon Platinum 8164''' is a {{arch|64}} [[x86]] high-performance server [[hexacosa-core]] [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 8164 operates at 2.0 GHz. |
+ | |||
+ | |||
+ | {{unknown features}} | ||
== Cache == | == Cache == | ||
− | {{main|intel/microarchitectures/ | + | {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} |
{{cache size | {{cache size | ||
|l1 cache=1.625 MiB | |l1 cache=1.625 MiB | ||
Line 65: | Line 130: | ||
|l3 cache=35.75 MiB | |l3 cache=35.75 MiB | ||
|l3 break=26x1.375 MiB | |l3 break=26x1.375 MiB | ||
− | |l3 desc= | + | |l3 desc=16-way set associative |
|l3 policy=write-back | |l3 policy=write-back | ||
}} | }} | ||
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|type=DDR4-2666 | |type=DDR4-2666 | ||
|ecc=Yes | |ecc=Yes | ||
− | |max mem= | + | |max mem= |
− | |controllers= | + | |controllers=1 |
|channels=6 | |channels=6 | ||
|max bandwidth=119.21 GiB/s | |max bandwidth=119.21 GiB/s | ||
− | |bandwidth schan=19. | + | |bandwidth schan=19.89 GiB/s |
− | |bandwidth dchan=39. | + | |bandwidth dchan=39.72 GiB/s |
|bandwidth qchan=79.47 GiB/s | |bandwidth qchan=79.47 GiB/s | ||
|bandwidth hchan=119.21 GiB/s | |bandwidth hchan=119.21 GiB/s | ||
}} | }} | ||
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