From WikiChip
Editing intel/xeon platinum/8160m

Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.

The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.

This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.

Latest revision Your text
Line 1: Line 1:
 
{{intel title|Xeon Platinum 8160M}}
 
{{intel title|Xeon Platinum 8160M}}
−
{{chip
+
{{mpu
−
|name=Xeon Platinum 8160M
+
| future              = Yes
−
|image=skylake sp (basic).png
+
| name               = Xeon Platinum 8160M
−
|designer=Intel
+
| no image            = Yes
−
|manufacturer=Intel
+
| image               =
−
|model number=8160M
+
| image size          =
−
|part number=CD8067303406600
+
| caption            =  
−
|s-spec=SR3B8
+
| designer           = Intel
−
|s-spec qs=QMS3
+
| manufacturer       = Intel
−
|market=Server
+
| model number       = 8160M
−
|first announced=April 25, 2017
+
| part number         = CD8067303406600
−
|first launched=July 11, 2017
+
| part number 1      =
−
|release price=$7704.00
+
| part number 2      =
−
|family=Xeon Platinum
+
| s-spec             = SR3B8
−
|series=8000
+
| s-spec 2            =  
−
|frequency=2,100 MHz
+
| market             = Server
−
|turbo frequency1=3,700 MHz
+
| first announced     = April 25, 2017
−
|clock multiplier=21
+
| first launched     =  
−
|cpuid=0x50654
+
| last order          =  
−
|isa=x86-64
+
| last shipment      =  
−
|isa family=x86
+
| release price      =  
−
|microarch=Skylake (server)
 
−
|platform=Purley
 
−
|chipset=Lewisburg
 
−
|core name=Skylake SP
 
−
|core family=6
 
−
|core stepping=H0
 
−
|process=14 nm
 
−
|technology=CMOS
 
−
|word size=64 bit
 
−
|core count=24
 
−
|thread count=48
 
−
|max cpus=8
 
−
|max memory=1,536 GiB
 
−
|tdp=150 W
 
−
|tcase min=0 °C
 
−
|tcase max=85 °C
 
−
|dts min=0 °C
 
−
|dts max=95 °C
 
−
|package name 1=intel,fclga_3647
 
−
|successor=Xeon Platinum 8260M
 
−
|successor link=intel/xeon_platinum/8260m
 
−
}}
 
−
'''Xeon Platinum 8160M''' is a {{arch|64}} [[24-core]] [[x86]] multi-socket highest performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 8-way multiprocessing. The Platinum 8160M, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.1 GHz with a TDP of 150 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 1.5 TiB of hexa-channel DDR4-2666 ECC memory.
 
−
 
 
−
As indicated by the ''M'' suffix, this specific model supports double the memory capacity for up to 1.5 TiB per socket.
 
−
 
 
−
== Cache ==
 
−
{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
 
−
{{cache size
 
−
|l1 cache=1.5 MiB
 
−
|l1i cache=768 KiB
 
−
|l1i break=24x32 KiB
 
−
|l1i desc=8-way set associative
 
−
|l1d cache=768 KiB
 
−
|l1d break=24x32 KiB
 
−
|l1d desc=8-way set associative
 
−
|l1d policy=write-back
 
−
|l2 cache=24 MiB
 
−
|l2 break=24x1 MiB
 
−
|l2 desc=16-way set associative
 
−
|l2 policy=write-back
 
−
|l3 cache=33 MiB
 
−
|l3 break=24x1.375 MiB
 
−
|l3 desc=11-way set associative
 
−
|l3 policy=write-back
 
−
}}
 
  
−
== Memory controller ==
+
| family              = Xeon Platinum
−
{{memory controller
+
| series              = 8100
−
|type=DDR4-2666
+
| locked              = Yes
−
|ecc=Yes
+
| frequency          = 2.1 GHz
−
|max mem=1,536 GiB
+
| turbo frequency    =
−
|controllers=2
+
| turbo frequency1    =
−
|channels=6
+
| turbo frequency2    =
−
|max bandwidth=119.21 GiB/s
+
| turbo frequency3    =
−
|bandwidth schan=19.87 GiB/s
+
| turbo frequency4    =  
−
|bandwidth dchan=39.74 GiB/s
+
| turbo frequency5    =  
−
|bandwidth qchan=79.47 GiB/s
+
| turbo frequency6    =  
−
|bandwidth hchan=119.21 GiB/s
+
| turbo frequency7    =  
−
}}
+
| turbo frequency8    =  
 +
| bus type            = DMI 3.0
 +
| bus speed          =  
 +
| bus rate            = 8 GT/s
 +
| bus links          = 4
 +
| clock multiplier    = 21
 +
| cpuid              =
 +
| cpuid 2            =
  
−
== Expansions ==
+
| isa family          = x86-64
−
{{expansions
+
| isa                = x86
−
| pcie revision      = 3.0
+
| microarch          = Skylake
−
| pcie lanes         = 48
+
| platform            = Purley
−
| pcie config       = x16
+
| chipset            = Lewisburg
−
| pcie config 2      = x8
+
| core name          = Skylake SP
−
| pcie config 3      = x4
+
| core family         =  
−
}}
+
| core model          =
 +
| core stepping      = H0
 +
| process            = 14 nm
 +
| transistors        =
 +
| technology          = CMOS
 +
| die area            = <!-- XX mm² -->
 +
| die width          =
 +
| die length          =
 +
| word size          = 64 bit
 +
| core count          =
 +
| thread count       =  
 +
| max cpus            = 8
 +
| max memory          =  
  
−
== Features ==
+
| electrical          =  
−
{{x86 features
+
| power              =  
−
|real=Yes
+
| average power      =  
−
|protected=Yes
+
| idle power          =  
−
|smm=Yes
+
| v core              =  
−
|fpu=Yes
+
| v core tolerance    = <!-- OR ... -->
−
|x8616=Yes
+
| v core min          =  
−
|x8632=Yes
+
| v core max          =  
−
|x8664=Yes
+
| v io                =  
−
|nx=Yes
+
| v io tolerance      =  
−
|mmx=Yes
+
| v io 2              = <!-- OR ... -->
−
|emmx=Yes
+
| v io 3              =  
−
|sse=Yes
+
| sdp                =  
−
|sse2=Yes
+
| tdp                =  
−
|sse3=Yes
+
| tdp typical        =  
−
|ssse3=Yes
+
| ctdp down          =  
−
|sse41=Yes
+
| ctdp down frequency =  
−
|sse42=Yes
+
| ctdp up            =  
−
|sse4a=No
+
| ctdp up frequency  =  
−
|avx=Yes
+
| temp min            = <!-- use TJ/TC whenever possible instead -->
−
|avx2=Yes
+
| temp max            =  
−
|avx512f=Yes
+
| tjunc min          = <!-- .. °C -->
−
|avx512cd=Yes
+
| tjunc max          =  
−
|avx512er=No
+
| tcase min          =  
−
|avx512pf=No
+
| tcase max          =  
−
|avx512bw=Yes
+
| tstorage min        =  
−
|avx512dq=Yes
+
| tstorage max        =  
−
|avx512vl=Yes
+
| tambient min        =  
−
|avx512ifma=No
+
| tambient max        =  
−
|avx512vbmi=No
 
−
|avx5124fmaps=No
 
−
|avx5124vnniw=No
 
−
|avx512vpopcntdq=No
 
−
|abm=Yes
 
−
|tbm=No
 
−
|bmi1=Yes
 
−
|bmi2=Yes
 
−
|fma3=Yes
 
−
|fma4=No
 
−
|aes=Yes
 
−
|rdrand=Yes
 
−
|sha=No
 
−
|xop=No
 
−
|adx=Yes
 
−
|clmul=Yes
 
−
|f16c=Yes
 
−
|tbt1=No
 
−
|tbt2=Yes
 
−
|tbmt3=No
 
−
|bpt=No
 
−
|eist=Yes
 
−
|sst=Yes
 
−
|flex=No
 
−
|fastmem=No
 
−
|ivmd=Yes
 
−
|intelnodecontroller=Yes
 
−
|intelnode=Yes
 
−
|kpt=Yes
 
−
|ptt=Yes
 
−
|intelrunsure=Yes
 
−
|mbe=Yes
 
−
|isrt=No
 
−
|sba=No
 
−
|mwt=No
 
−
|sipp=No
 
−
|att=No
 
−
|ipt=No
 
−
|tsx=Yes
 
−
|txt=Yes
 
−
|ht=Yes
 
−
|vpro=Yes
 
−
|vtx=Yes
 
−
|vtd=Yes
 
−
|ept=Yes
 
−
|mpx=No
 
−
|sgx=No
 
−
|securekey=No
 
−
|osguard=No
 
−
|3dnow=No
 
−
|e3dnow=No
 
−
|smartmp=No
 
−
|powernow=No
 
−
|amdvi=No
 
−
|amdv=No
 
−
|amdsme=No
 
−
|amdtsme=No
 
−
|amdsev=No
 
−
|rvi=No
 
−
|smt=No
 
−
|sensemi=No
 
−
|xfr=No
 
−
}}
 
  
−
== Frequencies ==
+
| package module 1   =  
−
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
+
| package module 2   =  
−
{{frequency table
+
<!-------- USE ONLY IF MUST, OTHERWISE TRY TO USE MODULE ABOVE -------------->
−
|freq_base=2,100 MHz
+
| packaging          = Yes
−
|freq_1=3,700 MHz
+
| package 0          = FCLGA-3647
−
|freq_2=3,700 MHz
+
| package 0 type      = LGA
−
|freq_3=3,500 MHz
+
| package 0 pins      = 3647
−
|freq_4=3,500 MHz
+
| package 0 pitch    =  
−
|freq_5=3,400 MHz
+
| package 0 width    =  
−
|freq_6=3,400 MHz
+
| package 0 length    =  
−
|freq_7=3,400 MHz
+
| package 0 height    =  
−
|freq_8=3,400 MHz
+
| socket 0            = LGA-3647
−
|freq_9=3,400 MHz
+
| socket 0 type      = LGA
−
|freq_10=3,400 MHz
 
−
|freq_11=3,400 MHz
 
−
|freq_12=3,400 MHz
 
−
|freq_13=3,200 MHz
 
−
|freq_14=3,200 MHz
 
−
|freq_15=3,200 MHz
 
−
|freq_16=3,200 MHz
 
−
|freq_17=3,000 MHz
 
−
|freq_18=3,000 MHz
 
−
|freq_19=3,000 MHz
 
−
|freq_20=3,000 MHz
 
−
|freq_21=2,800 MHz
 
−
|freq_22=2,800 MHz
 
−
|freq_23=2,800 MHz
 
−
|freq_24=2,800 MHz
 
−
|freq_avx2_base=1,800 MHz
 
−
|freq_avx2_1=3,600 MHz
 
−
|freq_avx2_2=3,600 MHz
 
−
|freq_avx2_3=3,400 MHz
 
−
|freq_avx2_4=3,400 MHz
 
−
|freq_avx2_5=3,300 MHz
 
−
|freq_avx2_6=3,300 MHz
 
−
|freq_avx2_7=3,300 MHz
 
−
|freq_avx2_8=3,300 MHz
 
−
|freq_avx2_9=3,200 MHz
 
−
|freq_avx2_10=3,200 MHz
 
−
|freq_avx2_11=3,200 MHz
 
−
|freq_avx2_12=3,200 MHz
 
−
|freq_avx2_13=2,900 MHz
 
−
|freq_avx2_14=2,900 MHz
 
−
|freq_avx2_15=2,900 MHz
 
−
|freq_avx2_16=2,900 MHz
 
−
|freq_avx2_17=2,600 MHz
 
−
|freq_avx2_18=2,600 MHz
 
−
|freq_avx2_19=2,600 MHz
 
−
|freq_avx2_20=2,600 MHz
 
−
|freq_avx2_21=2,500 MHz
 
−
|freq_avx2_22=2,500 MHz
 
−
|freq_avx2_23=2,500 MHz
 
−
|freq_avx2_24=2,500 MHz
 
−
|freq_avx512_base=1,400 MHz
 
−
|freq_avx512_1=3,500 MHz
 
−
|freq_avx512_2=3,500 MHz
 
−
|freq_avx512_3=3,300 MHz
 
−
|freq_avx512_4=3,300 MHz
 
−
|freq_avx512_5=3,000 MHz
 
−
|freq_avx512_6=3,000 MHz
 
−
|freq_avx512_7=3,000 MHz
 
−
|freq_avx512_8=3,000 MHz
 
−
|freq_avx512_9=2,600 MHz
 
−
|freq_avx512_10=2,600 MHz
 
−
|freq_avx512_11=2,600 MHz
 
−
|freq_avx512_12=2,600 MHz
 
−
|freq_avx512_13=2,300 MHz
 
−
|freq_avx512_14=2,300 MHz
 
−
|freq_avx512_15=2,300 MHz
 
−
|freq_avx512_16=2,300 MHz
 
−
|freq_avx512_17=2,100 MHz
 
−
|freq_avx512_18=2,100 MHz
 
−
|freq_avx512_19=2,100 MHz
 
−
|freq_avx512_20=2,100 MHz
 
−
|freq_avx512_21=2,000 MHz
 
−
|freq_avx512_22=2,000 MHz
 
−
|freq_avx512_23=2,000 MHz
 
−
|freq_avx512_24=2,000 MHz
 
 
}}
 
}}
−
 
−
[[Category:microprocessor models by intel based on skylake extreme core count die]]
 

Please note that all contributions to WikiChip may be edited, altered, or removed by other contributors. If you do not want your writing to be edited mercilessly, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource (see WikiChip:Copyrights for details). Do not submit copyrighted work without permission!

Cancel | Editing help (opens in new window)

Templates used on this page:

Retrieved from "https://en.wikichip.org/wiki/intel/xeon_platinum/8160m"
Facts about "Xeon Platinum 8160M - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon Platinum 8160M - Intel#io +
base frequency2,100 MHz (2.1 GHz, 2,100,000 kHz) +
chipsetLewisburg +
clock multiplier21 +
core count24 +
core family6 +
core nameSkylake SP +
core steppingH0 +
cpuid0x50654 +
designerIntel +
familyXeon Platinum +
first announcedApril 25, 2017 +
first launchedJuly 11, 2017 +
full page nameintel/xeon platinum/8160m +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Transactional Synchronization Extensions +, Extended Page Tables + and Advanced Vector Extensions 512 +
has intel enhanced speedstep technologytrue +
has intel speed shift technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size1,536 KiB (1,572,864 B, 1.5 MiB) +
l1d$ description8-way set associative +
l1d$ size768 KiB (786,432 B, 0.75 MiB) +
l1i$ description8-way set associative +
l1i$ size768 KiB (786,432 B, 0.75 MiB) +
l2$ description16-way set associative +
l2$ size24 MiB (24,576 KiB, 25,165,824 B, 0.0234 GiB) +
l3$ description11-way set associative +
l3$ size33 MiB (33,792 KiB, 34,603,008 B, 0.0322 GiB) +
ldateJuly 11, 2017 +
main imageFile:skylake sp (basic).png +
manufacturerIntel +
market segmentServer +
max case temperature358.15 K (85 °C, 185 °F, 644.67 °R) +
max cpu count8 +
max dts temperature95 °C +
max memory1,572,864 MiB (1,610,612,736 KiB, 1,649,267,441,664 B, 1,536 GiB, 1.5 TiB) +
max memory bandwidth119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels6 +
max pcie lanes48 +
microarchitectureSkylake (server) +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min dts temperature0 °C +
model number8160M +
nameXeon Platinum 8160M +
packageFCLGA-3647 +
part numberCD8067303406600 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 7,704.00 (€ 6,933.60, £ 6,240.24, ¥ 796,054.32) +
s-specSR3B8 +
s-spec (qs)QMS3 +
series8000 +
smp max ways8 +
socketSocket P + and LGA-3647 +
supported memory typeDDR4-2666 +
tdp150 W (150,000 mW, 0.201 hp, 0.15 kW) +
technologyCMOS +
thread count48 +
turbo frequency (1 core)3,700 MHz (3.7 GHz, 3,700,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +