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| | | isa = x86-64 | | | isa = x86-64 |
| | | microarch = Skylake | | | microarch = Skylake |
| − | | microarch 2 = Cascade Lake
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| − | | microarch 3 = Cooper Lake
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| | | word = 64 bit | | | word = 64 bit |
| | | proc = 14 nm | | | proc = 14 nm |
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| | == Overview == | | == Overview == |
| − | Introduced in May [[2017]], the Xeon Platinum family replaces the {{\\|Xeon E7}} and the {{\\|Xeon E5}} families. Xeon Platinum provides the highest performance and flexibility out of all the Xeon families, thus placing it above the {{\\|Xeon Gold}} and {{\\|Xeon Silver}} that were introduced around the same time. A specific feature available only to Platinum models is its eight-way multiprocessing support.
| + | {{empty section}} |
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| | == Members == | | == Members == |
| − | === 8000-Series === | + | === Skylake === |
| − | ==== 8100-Series (Skylake) ====
| + | {{see also|intel/microarchitectures/skylake|l1=Skylake µarch}} |
| − | {{see also|intel/microarchitectures/skylake (server)|l1=Skylake µarch}} | + | Introduced in July 2017, the {{intel|Skylake|l=arch}}-based Xeon Platinum microprocessors support eight-way [[multiprocessing]] with up to [[28 cores]] and 56 threads. Additionally, all Xeon Platinum processors support: |
| − | First-generation Xeon Platinum processors were introduced in July 2017. Those chips were fabricated on a enhanced [[14 nm process|14nm+ process]] based on the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture which brought a {{intel|Skylake (Server)#Key changes from Broadwell|l=arch|relatively large}} SoC design change from the prior Xeon families. Those processors were the first to move to a {{intel|mesh interconnect}} which introduced a tile-based architecture, bringing the first implementation of {{x86|AVX-512}} along with a rearchitected cache hierarchy designed for server workloads. All of the platinum 8100-series microprocessors feature eight-way [[SMP]] capabilities with up to [[28 cores]] and 56 threads. Additionally, all Xeon Platinum processors support:
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| − | * '''Proc:''' [[14 nm process]]
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| | * '''TDP:''' 105 W - 205 W | | * '''TDP:''' 105 W - 205 W |
| | * '''Mem:''' 768 GiB hexa-channel DDR4-2133 ECC memory. | | * '''Mem:''' 768 GiB hexa-channel DDR4-2133 ECC memory. |
| | ** ''M'' versions support 1.5 TiB per socket | | ** ''M'' versions support 1.5 TiB per socket |
| − | * '''I/O:''' 48 PCIe Gen 3.0 lanes | + | * '''I/O:''' 48 PCIe 3 lanes |
| − | * '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, {{x86|AVX-512}}-{{x86|AVX512F|F}}/{{x86|AVX512CD|CD}}/{{x86|AVX512BW|BW}}/{{x86|AVX512DQ|DQ}}/{{x86|AVX512VL|VL}}) | + | * '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX512F, AVX512CD, AVX512BW, AVX512DQ, AVX512VL) |
| | * '''Features:''' {{intel|Hyper-Threading}}, {{intel|Turbo Boost}}, {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Volume Management Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT). | | * '''Features:''' {{intel|Hyper-Threading}}, {{intel|Turbo Boost}}, {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Volume Management Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT). |
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| | {{comp table start}} | | {{comp table start}} |
| | <table class="comptable sortable tc4 tc5"> | | <table class="comptable sortable tc4 tc5"> |
| − | {{comp table header|main|11:List of Skylake-based Xeon Platinum Processors}}
| + | <tr class="comptable-header"><th> </th><th colspan="20">List of Skylake-based Xeon Platinum Processors</th></tr> |
| − | {{comp table header|main|7:Main processor|2:Cache|2:Memory}}
| + | <tr class="comptable-header"><th> </th><th colspan="7">Main processor</th><th colspan="2">Cache</th><th colspan="2">Memory</th></tr> |
| | {{comp table header 1|cols=Price, Launched, Cores, Threads, %Frequency, %Max Turbo, %TDP, %L2$, %L3$, Mem Type, %Max Mem}} | | {{comp table header 1|cols=Price, Launched, Cores, Threads, %Frequency, %Max Turbo, %TDP, %L2$, %L3$, Mem Type, %Max Mem}} |
| | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Platinum]] [[microarchitecture::Skylake (server)]] | | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Platinum]] [[microarchitecture::Skylake (server)]] |
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| | }} | | }} |
| | {{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Platinum]] [[microarchitecture::Skylake (server)]]}} | | {{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Platinum]] [[microarchitecture::Skylake (server)]]}} |
| − | </table>
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| − | {{comp table end}}
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| − |
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| − | ==== 8200-Series (Cascade Lake) ====
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| − | {{see also|intel/microarchitectures/cascade lake|l1=Cascade Lake µarch}}
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| − | Second-generation Xeon Scalable Platinum was introduced in early 2019. Those processors are fabricated on an enhanced [[14 nm process]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture which allows for higher clock speeds and introduced a {{intel|Cascade Lake#Key changes from Skylake|l=arch|number of}} hardware changes against the various [[speculative execution]] [[side channel analysis|vulnerabilities]]. Those processors also introduced new {{x86|AVX-512 VNNI|new instructions}} for the [[acceleration]] of machine learning (inference) as well as support for [[persistent memory]]. All 8200-series Xeon Platinum processors support:
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| − | * '''Proc:''' [[14 nm process]]
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| − | * '''TDP:''' 105 W - 205 W
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| − | * '''Mem:''' 1 TiB hexa-channel DDR4-2933 ECC memory
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| − | ** ''M'' versions support 2 TiB per socket
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| − | ** ''L'' versions support 4.5 TiB per socket
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| − | * '''I/O:''' 48 PCIe Gen 3.0 lanes
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| − | * '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, {{x86|AVX-512}}-{{x86|AVX512F|F}}/{{x86|AVX512CD|CD}}/{{x86|AVX512BW|BW}}/{{x86|AVX512DQ|DQ}}/{{x86|AVX512VL|VL}}/{{x86|AVX512VNNI|VNNI}})
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| − | * '''Features:''' {{intel|Hyper-Threading}}, {{intel|Turbo Boost}}, {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Volume Management Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT).
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| − |
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| − | All Xeon Platinum processors support QuickAssist Technology which is integrated on the chipset as well as the Omni-Path Architecture on the chipset as well as via discrete PCIe cards. All models also support 3 {{intel|Ultra Path Interconnect}} (UPI) links.
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| − |
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| − | <!-- NOTE:
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| − | This table is generated automatically from the data in the actual articles.
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| − | If a microprocessor is missing from the list, an appropriate article for it needs to be
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| − | created and tagged accordingly.
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| − |
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| − | Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
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| − | -->
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| − | {{comp table start}}
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| − | <table class="comptable sortable tc4 tc5">
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| − | {{comp table header|main|11:List of Cascade Lake-based Xeon Platinum Processors}}
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| − | {{comp table header|main|7:Main processor|2:Cache|2:Memory}}
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| − | {{comp table header 1|cols=Price, Launched, Cores, Threads, %Frequency, %Max Turbo, %TDP, %L2$, %L3$, Mem Type, %Max Mem}}
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| − | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Platinum]] [[microarchitecture::Cascade Lake]] [[series::8200]]
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| − | |?full page name
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| − | |?model number
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| − | |?release price
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| − | |?first launched
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| − | |?core count
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| − | |?thread count
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| − | |?base frequency#GHz
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| − | |?turbo frequency (1 core)#GHz
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| − | |?tdp
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| − | |?l2$ size
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| − | |?l3$ size
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| − | |?supported memory type
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| − | |?max memory#GiB
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| − | |format=template
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| − | |template=proc table 3
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| − | |valuesep=,
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| − | |userparam=13
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| − | |mainlabel=-
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| − | }}
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| − | {{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Platinum]] [[microarchitecture::Cascade Lake]] [[series::8200]]}}
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| − | </table>
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| − | {{comp table end}}
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| − |
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| − | === 9000-Series ===
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| − | ==== 9200-Series (Cascade Lake) ====
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| − | [[File:cascade lake ap board.JPG|right|thumb|Cascade Lake AP S9200WK module]]
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| − | {{see also|intel/microarchitectures/cascade lake|l1=Cascade Lake µarch}}
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| − | Along with its mainstream second-generation Xeon Scalable Platinum processors, Intel introduced the 9200 series, codenamed {{intel|Cascade Lake AP|l=core}}. The chips incorporate multiple {{intel|Cascade Lake|l=arch}} dies in a [[multi-chip package]], enabling up to 56 cores in a single socket. In other words, the 9200 series incorporates two 8200 series chips in a single socket, doubling the density. It's important to note that those processors cannot be purchased individually. Instead, they can only be bought as part of Intel's S9200WK compute module which is essentially a complete system designed by Intel.
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| − |
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| − | * '''Proc:''' [[14 nm process]]
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| − | * '''TDP:''' 250 W - 400 W
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| − | * '''Mem:''' 2 TiB hexa-channel DDR4-2933 ECC memory
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| − | * '''I/O:''' x40 Lanes of PCIe Gen 3 (limited by the S9200WK module, actual models support more lanes but are not sold independently)
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| − | * '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, {{x86|AVX-512}}-{{x86|AVX512F|F}}/{{x86|AVX512CD|CD}}/{{x86|AVX512BW|BW}}/{{x86|AVX512DQ|DQ}}/{{x86|AVX512VL|VL}}/{{x86|AVX512VNNI|VNNI}})
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| − | * '''Features:''' {{intel|Hyper-Threading}}, {{intel|Turbo Boost}}, {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Volume Management Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT).
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| − |
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| − | <!-- NOTE:
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| − | This table is generated automatically from the data in the actual articles.
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| − | If a microprocessor is missing from the list, an appropriate article for it needs to be
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| − | created and tagged accordingly.
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| − |
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| − | Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
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| − | -->
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| − | {{comp table start}}
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| − | <table class="comptable sortable tc3 tc4 tc5 tc6">
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| − | {{comp table header|main|11:List of Cascade Lake AP-based Xeon Platinum Processors}}
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| − | {{comp table header|main|7:Main processor|2:Cache|2:Memory}}
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| − | {{comp table header 1|cols=Launched, Cores, Threads, %Frequency, %Max Turbo, %TDP, %L2$, %L3$, Mem Type, %Max Mem}}
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| − | {{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake AP]]
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| − | |?full page name
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| − | |?model number
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| − | |?first launched
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| − | |?core count
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| − | |?thread count
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| − | |?base frequency#GHz
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| − | |?turbo frequency (1 core)#GHz
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| − | |?tdp
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| − | |?l2$ size
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| − | |?l3$ size
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| − | |?supported memory type
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| − | |?max memory#GiB
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| − | |format=template
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| − | |template=proc table 3
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| − | |valuesep=,
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| − | |userparam=12
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| − | |mainlabel=-
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| − | }}
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| − | {{comp table count|ask=[[Category:microprocessor models by intel]] [[core name::Cascade Lake AP]]}}
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| | </table> | | </table> |
| | {{comp table end}} | | {{comp table end}} |
