From WikiChip
Editing intel/xeon gold/6246

Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.

The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.

This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.

Latest revision Your text
Line 6: Line 6:
 
|manufacturer=Intel
 
|manufacturer=Intel
 
|model number=6246
 
|model number=6246
|s-spec qs=QS1Q
 
 
|market=Server
 
|market=Server
 
|first announced=April 2, 2019
 
|first announced=April 2, 2019
Line 28: Line 27:
 
|core family=6
 
|core family=6
 
|core model=85
 
|core model=85
|core stepping=B1
 
 
|process=14 nm
 
|process=14 nm
 
|technology=CMOS
 
|technology=CMOS
Line 34: Line 32:
 
|core count=12
 
|core count=12
 
|thread count=24
 
|thread count=24
 +
|max cpus=4
 
|max memory=1 TiB
 
|max memory=1 TiB
|max cpus=4
 
|smp interconnect=UPI
 
|smp interconnect links=3
 
|smp interconnect rate=10.4 GT/s
 
 
|tdp=165 W
 
|tdp=165 W
 
|tcase min=0 °C
 
|tcase min=0 °C
 
|tcase max=76 °C
 
|tcase max=76 °C
 
|package name 1=intel,fclga_3647
 
|package name 1=intel,fclga_3647
|predecessor=Xeon Gold 6146
 
|predecessor link=intel/xeon_gold/6146
 
 
}}
 
}}
 
'''Xeon Gold 6246''' is a {{arch|64}} [[12-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 6246 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.3 GHz with a TDP of 165 W and features a {{intel|turbo boost}} frequency of up to 4.2 GHz.
 
'''Xeon Gold 6246''' is a {{arch|64}} [[12-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 6246 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.3 GHz with a TDP of 165 W and features a {{intel|turbo boost}} frequency of up to 4.2 GHz.
Line 198: Line 191:
 
|amdpb2=No
 
|amdpb2=No
 
|amdpbod=No
 
|amdpbod=No
}}
 
 
== Frequencies ==
 
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 
{{frequency table
 
|freq_base=3,300MHz
 
|freq_1=4,200MHz
 
|freq_2=4,200MHz
 
|freq_3=4,100MHz
 
|freq_4=4,100MHz
 
|freq_5=4,100MHz
 
|freq_6=4,100MHz
 
|freq_7=4,100MHz
 
|freq_8=4,100MHz
 
|freq_9=4,100MHz
 
|freq_10=4,100MHz
 
|freq_11=4,100MHz
 
|freq_12=4,100MHz
 
|freq_avx2_base=2,900MHz
 
|freq_avx2_1=4,000MHz
 
|freq_avx2_2=4,000MHz
 
|freq_avx2_3=3,800MHz
 
|freq_avx2_4=3,800MHz
 
|freq_avx2_5=3,800MHz
 
|freq_avx2_6=3,800MHz
 
|freq_avx2_7=3,800MHz
 
|freq_avx2_8=3,800MHz
 
|freq_avx2_9=3,800MHz
 
|freq_avx2_10=3,800MHz
 
|freq_avx2_11=3,800MHz
 
|freq_avx2_12=3,800MHz
 
|freq_avx512_base=2,400MHz
 
|freq_avx512_1=3,900MHz
 
|freq_avx512_2=3,900MHz
 
|freq_avx512_3=3,700MHz
 
|freq_avx512_4=3,700MHz
 
|freq_avx512_5=3,600MHz
 
|freq_avx512_6=3,600MHz
 
|freq_avx512_7=3,600MHz
 
|freq_avx512_8=3,600MHz
 
|freq_avx512_9=3,400MHz
 
|freq_avx512_10=3,400MHz
 
|freq_avx512_11=3,400MHz
 
|freq_avx512_12=3,400MHz
 
 
}}
 
}}

Please note that all contributions to WikiChip may be edited, altered, or removed by other contributors. If you do not want your writing to be edited mercilessly, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource (see WikiChip:Copyrights for details). Do not submit copyrighted work without permission!

Cancel | Editing help (opens in new window)
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon Gold 6246 - Intel#pcie +
base frequency3,300 MHz (3.3 GHz, 3,300,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typeDMI 3.0 +
chipsetLewisburg +
clock multiplier33 +
core count12 +
core family6 +
core model85 +
core nameCascade Lake SP +
core steppingB1 +
designerIntel +
familyXeon Gold +
first announcedApril 2, 2019 +
first launchedApril 2, 2019 +
full page nameintel/xeon gold/6246 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions + and Deep Learning Boost +
has intel deep learning boosttrue +
has intel enhanced speedstep technologytrue +
has intel speed shift technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size768 KiB (786,432 B, 0.75 MiB) +
l1d$ description8-way set associative +
l1d$ size384 KiB (393,216 B, 0.375 MiB) +
l1i$ description8-way set associative +
l1i$ size384 KiB (393,216 B, 0.375 MiB) +
l2$ description16-way set associative +
l2$ size12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) +
l3$ description11-way set associative +
l3$ size24.75 MiB (25,344 KiB, 25,952,256 B, 0.0242 GiB) +
ldateApril 2, 2019 +
main imageFile:cascade lake sp (front).png +
manufacturerIntel +
market segmentServer +
max case temperature349.15 K (76 °C, 168.8 °F, 628.47 °R) +
max cpu count4 +
max memory1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
max memory bandwidth131.13 GiB/s (134,277.12 MiB/s, 140.8 GB/s, 140,799.765 MB/s, 0.128 TiB/s, 0.141 TB/s) +
max memory channels6 +
microarchitectureCascade Lake +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model number6246 +
nameXeon Gold 6246 +
packageFCLGA-3647 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 3,286.00 (€ 2,957.40, £ 2,661.66, ¥ 339,542.38) +
release price (tray)$ 3,286.00 (€ 2,957.40, £ 2,661.66, ¥ 339,542.38) +
s-spec (qs)QS1Q +
series6200 +
smp interconnectUPI +
smp interconnect links3 +
smp interconnect rate10.4 GT/s +
smp max ways4 +
socketSocket P + and LGA-3647 +
supported memory typeDDR4-2933 +
tdp165 W (165,000 mW, 0.221 hp, 0.165 kW) +
technologyCMOS +
thread count24 +
turbo frequency (1 core)4,200 MHz (4.2 GHz, 4,200,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +