From WikiChip
Editing intel/xeon gold/6152

Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.

The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.

This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.

Latest revision Your text
Line 1: Line 1:
 
{{intel title|Xeon Gold 6152}}
 
{{intel title|Xeon Gold 6152}}
{{chip
+
{{mpu
 
|name=Xeon Gold 6152
 
|name=Xeon Gold 6152
 
|image=skylake sp (basic).png
 
|image=skylake sp (basic).png
Line 9: Line 9:
 
|part number 2=CD8067303406000
 
|part number 2=CD8067303406000
 
|s-spec=SR3B4
 
|s-spec=SR3B4
|s-spec qs=QMRZ
 
 
|market=Server
 
|market=Server
 
|first announced=April 25, 2017
 
|first announced=April 25, 2017
Line 15: Line 14:
 
|release price=$3655.00
 
|release price=$3655.00
 
|family=Xeon Gold
 
|family=Xeon Gold
|series=6100
+
|series=6000
 
|locked=Yes
 
|locked=Yes
 
|frequency=2,100 MHz
 
|frequency=2,100 MHz
 
|turbo frequency1=3,700 MHz
 
|turbo frequency1=3,700 MHz
 
|clock multiplier=21
 
|clock multiplier=21
|cpuid=0x50654
 
 
|isa=x86-64
 
|isa=x86-64
 
|isa family=x86
 
|isa family=x86
|microarch=Skylake (server)
+
|microarch=Skylake
 
|platform=Purley
 
|platform=Purley
 
|chipset=Lewisburg
 
|chipset=Lewisburg
Line 34: Line 32:
 
|core count=22
 
|core count=22
 
|thread count=44
 
|thread count=44
 +
|max cpus=4
 
|max memory=768 GiB
 
|max memory=768 GiB
|max cpus=4
 
|smp interconnect=UPI
 
|smp interconnect links=3
 
|smp interconnect rate=10.4 GT/s
 
 
|tdp=140 W
 
|tdp=140 W
 
|tcase min=0 °C
 
|tcase min=0 °C
 
|tcase max=92 °C
 
|tcase max=92 °C
|dts min=0 °C
+
|package module 1={{packages/intel/fclga-3647}}
|dts max=98  °C
 
|package name 1=intel,fclga_3647
 
|successor=Xeon Gold 6252
 
|successor link=intel/xeon_gold/6252
 
 
}}
 
}}
'''Xeon Gold 6152''' is a {{arch|64}} [[22-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6152, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.1 GHz with a TDP of 140 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
+
'''Xeon Gold 6152''' is a {{arch|64}} [[22-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6152, which is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.1 GHz with a TDP of 140 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
  
 
== Cache ==
 
== Cache ==
{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
+
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
 
{{cache size
 
{{cache size
|l1 cache=1.375 MiB
+
|l1 cache=1.25 MiB
|l1i cache=704 KiB
+
|l1i cache=640 KiB
|l1i break=22x32 KiB
+
|l1i break=20x32 KiB
 
|l1i desc=8-way set associative
 
|l1i desc=8-way set associative
|l1d cache=704 KiB
+
|l1d cache=640 KiB
|l1d break=22x32 KiB
+
|l1d break=20x32 KiB
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
 
|l1d policy=write-back
 
|l1d policy=write-back
|l2 cache=22 MiB
+
|l2 cache=20 MiB
|l2 break=22x1 MiB
+
|l2 break=20x1 MiB
 
|l2 desc=16-way set associative
 
|l2 desc=16-way set associative
 
|l2 policy=write-back
 
|l2 policy=write-back
|l3 cache=30.25 MiB
+
|l3 cache=27.5 MiB
|l3 break=22x1.375 MiB
+
|l3 break=20x1.375 MiB
 
|l3 desc=11-way set associative
 
|l3 desc=11-way set associative
 
|l3 policy=write-back
 
|l3 policy=write-back
Line 186: Line 177:
 
|xfr=No
 
|xfr=No
 
}}
 
}}
 
== Frequencies ==
 
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 
{{frequency table
 
|freq_base=2,100 MHz
 
|freq_1=3,700 MHz
 
|freq_2=3,700 MHz
 
|freq_3=3,500 MHz
 
|freq_4=3,500 MHz
 
|freq_5=3,400 MHz
 
|freq_6=3,400 MHz
 
|freq_7=3,400 MHz
 
|freq_8=3,400 MHz
 
|freq_9=3,400 MHz
 
|freq_10=3,400 MHz
 
|freq_11=3,400 MHz
 
|freq_12=3,400 MHz
 
|freq_13=3,100 MHz
 
|freq_14=3,100 MHz
 
|freq_15=3,100 MHz
 
|freq_16=3,100 MHz
 
|freq_17=2,900 MHz
 
|freq_18=2,900 MHz
 
|freq_19=2,900 MHz
 
|freq_20=2,900 MHz
 
|freq_21=2,800 MHz
 
|freq_22=2,800 MHz
 
|freq_avx2_base=1,700 MHz
 
|freq_avx2_1=3,600 MHz
 
|freq_avx2_2=3,600 MHz
 
|freq_avx2_3=3,400 MHz
 
|freq_avx2_4=3,400 MHz
 
|freq_avx2_5=3,300 MHz
 
|freq_avx2_6=3,300 MHz
 
|freq_avx2_7=3,300 MHz
 
|freq_avx2_8=3,300 MHz
 
|freq_avx2_9=3,000 MHz
 
|freq_avx2_10=3,000 MHz
 
|freq_avx2_11=3,000 MHz
 
|freq_avx2_12=3,000 MHz
 
|freq_avx2_13=2,700 MHz
 
|freq_avx2_14=2,700 MHz
 
|freq_avx2_15=2,700 MHz
 
|freq_avx2_16=2,700 MHz
 
|freq_avx2_17=2,400 MHz
 
|freq_avx2_18=2,400 MHz
 
|freq_avx2_19=2,400 MHz
 
|freq_avx2_20=2,400 MHz
 
|freq_avx2_21=2,400 MHz
 
|freq_avx2_22=2,400 MHz
 
|freq_avx512_base=1,400 MHz
 
|freq_avx512_1=3,500 MHz
 
|freq_avx512_2=3,500 MHz
 
|freq_avx512_3=3,300 MHz
 
|freq_avx512_4=3,300 MHz
 
|freq_avx512_5=2,900 MHz
 
|freq_avx512_6=2,900 MHz
 
|freq_avx512_7=2,900 MHz
 
|freq_avx512_8=2,900 MHz
 
|freq_avx512_9=2,500 MHz
 
|freq_avx512_10=2,500 MHz
 
|freq_avx512_11=2,500 MHz
 
|freq_avx512_12=2,500 MHz
 
|freq_avx512_13=2,200 MHz
 
|freq_avx512_14=2,200 MHz
 
|freq_avx512_15=2,200 MHz
 
|freq_avx512_16=2,200 MHz
 
|freq_avx512_17=2,000 MHz
 
|freq_avx512_18=2,000 MHz
 
|freq_avx512_19=2,000 MHz
 
|freq_avx512_20=2,000 MHz
 
|freq_avx512_21=2,000 MHz
 
|freq_avx512_22=2,000 MHz
 
}}
 
 
== Benchmarks ==
 
{{benchmarks main
 
|
 
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00358.html|test_timestamp=2017-10-16 01:45:46-0400|chip_count=2|core_count=44|copies_count=88|vendor=HPE|system=ProLiant DL380 Gen10 (2.10 GHz, Intel Xeon Gold 6152)|SPECrate2017_int_base=210|SPECrate2017_int_peak=}}
 
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00359.html|test_timestamp=2017-10-12 05:59:17-0400|chip_count=2|core_count=44|thread_count=44|vendor=HPE|system=ProLiant DL380 Gen10 (2.10 GHz, Intel Xeon Gold 6152)|SPECspeed2017_fp_base=114|SPECspeed2017_fp_peak=}}
 
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00360.html|test_timestamp=2017-10-16 07:22:47-0400|chip_count=2|core_count=44|copies_count=88|vendor=HPE|system=ProLiant DL380 Gen10 (2.10 GHz, Intel Xeon Gold 6152)|SPECrate2017_fp_base=197|SPECrate2017_fp_peak=}}
 
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00478.html|test_timestamp=2017-10-12 02:57:28-0400|chip_count=2|core_count=44|thread_count=44|vendor=HPE|system=ProLiant DL380 Gen10 (2.10 GHz, Intel Xeon Gold 6152)|SPECspeed2017_int_base=8.89|SPECspeed2017_int_peak=}}
 
}}
 
 
[[Category:microprocessor models by intel based on skylake extreme core count die]]
 

Please note that all contributions to WikiChip may be edited, altered, or removed by other contributors. If you do not want your writing to be edited mercilessly, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource (see WikiChip:Copyrights for details). Do not submit copyrighted work without permission!

Cancel | Editing help (opens in new window)
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon Gold 6152 - Intel +, Xeon Gold 6152 - Intel +, Xeon Gold 6152 - Intel +, Xeon Gold 6152 - Intel + and Xeon Gold 6152 - Intel#io +
base frequency2,100 MHz (2.1 GHz, 2,100,000 kHz) +
chipsetLewisburg +
clock multiplier21 +
core count22 +
core family6 +
core nameSkylake SP +
core steppingH0 +
cpuid0x50654 +
designerIntel +
familyXeon Gold +
first announcedApril 25, 2017 +
first launchedJuly 11, 2017 +
full page nameintel/xeon gold/6152 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Transactional Synchronization Extensions +, Turbo Boost Technology 2.0 +, Speed Shift Technology +, Trusted Execution Technology +, Extended Page Tables + and Advanced Vector Extensions 512 +
has intel enhanced speedstep technologytrue +
has intel speed shift technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size1,408 KiB (1,441,792 B, 1.375 MiB) +
l1d$ description8-way set associative +
l1d$ size704 KiB (720,896 B, 0.688 MiB) +
l1i$ description8-way set associative +
l1i$ size704 KiB (720,896 B, 0.688 MiB) +
l2$ description16-way set associative +
l2$ size22 MiB (22,528 KiB, 23,068,672 B, 0.0215 GiB) +
l3$ description11-way set associative +
l3$ size30.25 MiB (30,976 KiB, 31,719,424 B, 0.0295 GiB) +
ldateJuly 11, 2017 +
main imageFile:skylake sp (basic).png +
manufacturerIntel +
market segmentServer +
max case temperature365.15 K (92 °C, 197.6 °F, 657.27 °R) +
max cpu count4 +
max dts temperature98 °C +
max memory786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) +
max memory bandwidth119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels6 +
max pcie lanes48 +
microarchitectureSkylake (server) +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min dts temperature0 °C +
model number6152 +
nameXeon Gold 6152 +
packageFCLGA-3647 +
part numberCD8067303406000 + and BX806736152 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 3,655.00 (€ 3,289.50, £ 2,960.55, ¥ 377,671.15) +
s-specSR3B4 +
s-spec (qs)QMRZ +
series6100 +
smp interconnectUPI +
smp interconnect links3 +
smp interconnect rate10.4 GT/s +
smp max ways4 +
socketSocket P + and LGA-3647 +
supported memory typeDDR4-2666 +
tdp140 W (140,000 mW, 0.188 hp, 0.14 kW) +
technologyCMOS +
thread count44 +
turbo frequency (1 core)3,700 MHz (3.7 GHz, 3,700,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +