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{{intel title|Xeon Gold 6136}}
 
{{intel title|Xeon Gold 6136}}
−
{{chip
+
{{mpu
−
|name=Xeon Gold 6136
+
| future              = Yes
−
|image=skylake sp (basic).png
+
| name               = Xeon Gold 6136
−
|designer=Intel
+
| no image            = Yes
−
|manufacturer=Intel
+
| image              =
−
|model number=6136
+
| image size          =
−
|part number=CD8067303405800
+
| caption            =  
−
|s-spec=SR3B2
+
| designer           = Intel
−
|s-spec qs=QMRX
+
| manufacturer       = Intel
−
|market=Server
+
| model number       = 6136
−
|first announced=April 25, 2017
+
| part number         = CD8067303405800
−
|first launched=July 11, 2017
+
| part number 1      =
−
|release price=$2460.00
+
| part number 2      =
−
|family=Xeon Gold
+
| s-spec             = SR3B2
−
|series=6100
+
| s-spec 2            =  
−
|locked=Yes
+
| market             = Server
−
|frequency=3,000 MHz
+
| first announced     = April 25, 2017
−
|turbo frequency1=3,700 MHz
+
| first launched     =  
−
|bus type=DMI 3.0
+
| last order          =  
−
|bus links=4
+
| last shipment      =  
−
|bus rate=8 GT/s
+
| release price      =  
−
|clock multiplier=30
 
−
|cpuid=0x50654
 
−
|isa=x86-64
 
−
|isa family=x86
 
−
|microarch=Skylake (server)
 
−
|platform=Purley
 
−
|chipset=Lewisburg
 
−
|core name=Skylake SP
 
−
|core family=6
 
−
|core stepping=H0
 
−
|process=14 nm
 
−
|technology=CMOS
 
−
|word size=64 bit
 
−
|core count=12
 
−
|thread count=24
 
−
|max memory=768 GiB
 
−
|max cpus=4
 
−
|smp interconnect=UPI
 
−
|smp interconnect links=3
 
−
|smp interconnect rate=10.4 GT/s
 
−
|tdp=150 W
 
−
|tcase min=0 °C
 
−
|tcase max=85 °C
 
−
|dts min=0 °C
 
−
|dts max=103 °C
 
−
|package name 1=intel,fclga_3647
 
−
}}
 
−
'''Xeon Gold 6136''' is a {{arch|64}} [[dodeca-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6136, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 3 GHz with a TDP of 150 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
 
  
−
== Cache ==
+
| family              = Xeon Gold
−
{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
+
| series              = 6100
−
The Xeon Gold 6136 features a considerably larger non-default 24.75 MiB of [[L3]], a size that would normally be found on an 18-core part.
+
| locked              = Yes
−
{{cache size
+
| frequency          = 3.0 GHz
−
|l1 cache=768 KiB
+
| turbo frequency    =  
−
|l1i cache=384 KiB
+
| turbo frequency1    =  
−
|l1i break=12x32 KiB
+
| turbo frequency2    =  
−
|l1i desc=8-way set associative
+
| turbo frequency3    =  
−
|l1d cache=384 KiB
+
| turbo frequency4    =  
−
|l1d break=12x32 KiB
+
| turbo frequency5    =  
−
|l1d desc=8-way set associative
+
| turbo frequency6    =  
−
|l1d policy=write-back
+
| turbo frequency7    =  
−
|l2 cache=12 MiB
+
| turbo frequency8    =  
−
|l2 break=12x1 MiB
+
| bus type            = DMI 3.0
−
|l2 desc=16-way set associative
+
| bus speed          =  
−
|l2 policy=write-back
+
| bus rate            = 8 GT/s
−
|l3 cache=24.75 MiB
+
| bus links          = 4
−
|l3 break=18x1.375 MiB
+
| clock multiplier    = 30
−
|l3 desc=11-way set associative
+
| cpuid              =  
−
|l3 policy=write-back
+
| cpuid 2            =  
−
}}
 
  
−
== Memory controller ==
+
| isa family          = x86-64
−
{{memory controller
+
| isa                = x86
−
|type=DDR4-2666
+
| microarch          = Skylake
−
|ecc=Yes
+
| platform            = Purley
−
|max mem=768 GiB
+
| chipset            = Lewisburg
−
|controllers=2
+
| core name          = Skylake SP
−
|channels=6
+
| core family        =  
−
|max bandwidth=119.21 GiB/s
+
| core model          =
−
|bandwidth schan=19.87 GiB/s
+
| core stepping      = H0
−
|bandwidth dchan=39.74 GiB/s
+
| process            = 14 nm
−
|bandwidth qchan=79.47 GiB/s
+
| transistors        =  
−
|bandwidth hchan=119.21 GiB/s
+
| technology          = CMOS
−
}}
+
| die area            = <!-- XX mm² -->
 +
| die width          =
 +
| die length          =  
 +
| word size          = 64 bit
 +
| core count          =  
 +
| thread count        =  
 +
| max cpus            = 4
 +
| max memory          =
  
−
== Expansions ==
+
| electrical          =  
−
{{expansions
+
| power              =  
−
| pcie revision     = 3.0
+
| average power      =  
−
| pcie lanes        = 48
+
| idle power          =  
−
| pcie config       = x16
+
| v core              =
−
| pcie config 2      = x8
+
| v core tolerance    = <!-- OR ... -->
−
| pcie config 3      = x4
+
| v core min          =
−
}}
+
| v core max          =
 +
| v io                =
 +
| v io tolerance     =  
 +
| v io 2              = <!-- OR ... -->
 +
| v io 3             =
 +
| sdp                =
 +
| tdp                =
 +
| tdp typical        =
 +
| ctdp down          =
 +
| ctdp down frequency =
 +
| ctdp up            =
 +
| ctdp up frequency  =
 +
| temp min            = <!-- use TJ/TC whenever possible instead -->
 +
| temp max            =
 +
| tjunc min          = <!-- .. °C -->
 +
| tjunc max          =
 +
| tcase min          =
 +
| tcase max          =  
 +
| tstorage min       =  
 +
| tstorage max        =  
 +
| tambient min        =  
 +
| tambient max        =
  
−
== Features ==
+
| package module 1    =  
−
{{x86 features
+
| package module 2    =  
−
|real=Yes
+
<!-------- USE ONLY IF MUST, OTHERWISE TRY TO USE MODULE ABOVE -------------->
−
|protected=Yes
+
| packaging          = Yes
−
|smm=Yes
+
| package 0          = FCLGA-3647
−
|fpu=Yes
+
| package 0 type      = LGA
−
|x8616=Yes
+
| package 0 pins      = 3647
−
|x8632=Yes
+
| package 0 pitch    =  
−
|x8664=Yes
+
| package 0 width    =  
−
|nx=Yes
+
| package 0 length    =  
−
|mmx=Yes
+
| package 0 height    =  
−
|emmx=Yes
+
| socket 0            = LGA-3647
−
|sse=Yes
+
| socket 0 type      = LGA
−
|sse2=Yes
 
−
|sse3=Yes
 
−
|ssse3=Yes
 
−
|sse41=Yes
 
−
|sse42=Yes
 
−
|sse4a=No
 
−
|avx=Yes
 
−
|avx2=Yes
 
−
|avx512f=Yes
 
−
|avx512cd=Yes
 
−
|avx512er=No
 
−
|avx512pf=No
 
−
|avx512bw=Yes
 
−
|avx512dq=Yes
 
−
|avx512vl=Yes
 
−
|avx512ifma=No
 
−
|avx512vbmi=No
 
−
|avx5124fmaps=No
 
−
|avx5124vnniw=No
 
−
|avx512vpopcntdq=No
 
−
|abm=Yes
 
−
|tbm=No
 
−
|bmi1=Yes
 
−
|bmi2=Yes
 
−
|fma3=Yes
 
−
|fma4=No
 
−
|aes=Yes
 
−
|rdrand=Yes
 
−
|sha=No
 
−
|xop=No
 
−
|adx=Yes
 
−
|clmul=Yes
 
−
|f16c=Yes
 
−
|tbt1=No
 
−
|tbt2=Yes
 
−
|tbmt3=No
 
−
|bpt=No
 
−
|eist=Yes
 
−
|sst=Yes
 
−
|flex=No
 
−
|fastmem=No
 
−
|ivmd=Yes
 
−
|intelnodecontroller=Yes
 
−
|intelnode=Yes
 
−
|kpt=Yes
 
−
|ptt=Yes
 
−
|intelrunsure=Yes
 
−
|mbe=Yes
 
−
|isrt=No
 
−
|sba=No
 
−
|mwt=No
 
−
|sipp=No
 
−
|att=No
 
−
|ipt=No
 
−
|tsx=Yes
 
−
|txt=Yes
 
−
|ht=Yes
 
−
|vpro=Yes
 
−
|vtx=Yes
 
−
|vtd=Yes
 
−
|ept=Yes
 
−
|mpx=No
 
−
|sgx=No
 
−
|securekey=No
 
−
|osguard=No
 
−
|3dnow=No
 
−
|e3dnow=No
 
−
|smartmp=No
 
−
|powernow=No
 
−
|amdvi=No
 
−
|amdv=No
 
−
|amdsme=No
 
−
|amdtsme=No
 
−
|amdsev=No
 
−
|rvi=No
 
−
|smt=No
 
−
|sensemi=No
 
−
|xfr=No
 
 
}}
 
}}
 +
'''Xeon Gold 6136''' is a {{arch|64}} [[x86]] high-performance server [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 6136 operates at 3.0 GHz
  
−
== Frequencies ==
 
−
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 
−
{{frequency table
 
−
|freq_base=3,000 MHz
 
−
|freq_1=3,700 MHz
 
−
|freq_2=3,700 MHz
 
−
|freq_3=3,600 MHz
 
−
|freq_4=3,600 MHz
 
−
|freq_5=3,600 MHz
 
−
|freq_6=3,600 MHz
 
−
|freq_7=3,600 MHz
 
−
|freq_8=3,600 MHz
 
−
|freq_9=3,600 MHz
 
−
|freq_10=3,600 MHz
 
−
|freq_11=3,600 MHz
 
−
|freq_12=3,600 MHz
 
−
|freq_avx2_base=2,600 MHz
 
−
|freq_avx2_1=3,600 MHz
 
−
|freq_avx2_2=3,600 MHz
 
−
|freq_avx2_3=3,400 MHz
 
−
|freq_avx2_4=3,400 MHz
 
−
|freq_avx2_5=3,300 MHz
 
−
|freq_avx2_6=3,300 MHz
 
−
|freq_avx2_7=3,300 MHz
 
−
|freq_avx2_8=3,300 MHz
 
−
|freq_avx2_9=3,300 MHz
 
−
|freq_avx2_10=3,300 MHz
 
−
|freq_avx2_11=3,300 MHz
 
−
|freq_avx2_12=3,300 MHz
 
−
|freq_avx512_base=2,100 MHz
 
−
|freq_avx512_1=3,500 MHz
 
−
|freq_avx512_2=3,500 MHz
 
−
|freq_avx512_3=3,300 MHz
 
−
|freq_avx512_4=3,300 MHz
 
−
|freq_avx512_5=3,100 MHz
 
−
|freq_avx512_6=3,100 MHz
 
−
|freq_avx512_7=3,100 MHz
 
−
|freq_avx512_8=3,100 MHz
 
−
|freq_avx512_9=2,700 MHz
 
−
|freq_avx512_10=2,700 MHz
 
−
|freq_avx512_11=2,700 MHz
 
−
|freq_avx512_12=2,700 MHz
 
−
}}
 
−
 
−
== Benchmarks ==
 
−
{{benchmarks main
 
−
|
 
−
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171017-00145.html|test_timestamp=2017-10-07 20:52:23-0400|chip_count=2|core_count=24|copies_count=48|vendor=HPE|system=ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)|SPECrate2017_fp_base=159|SPECrate2017_fp_peak=}}
 
−
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171017-00149.html|test_timestamp=2017-10-13 04:45:58-0400|chip_count=2|core_count=24|thread_count=24|vendor=HPE|system=ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)|SPECspeed2017_fp_base=103|SPECspeed2017_fp_peak=}}
 
−
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171017-00155.html|test_timestamp=2017-10-13 05:57:20-0400|chip_count=2|core_count=24|thread_count=24|vendor=HPE|system=ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)|SPECspeed2017_int_base=8.8|SPECspeed2017_int_peak=}}
 
−
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171017-00206.html|test_timestamp=2017-10-07 16:38:18-0400|chip_count=2|core_count=24|copies_count=48|vendor=HPE|system=ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)|SPECrate2017_int_base=149|SPECrate2017_int_peak=}}
 
−
}}
 
  
−
[[Category:microprocessor models by intel based on skylake extreme core count die]]
+
{{unknown features}}

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Retrieved from "https://en.wikichip.org/wiki/intel/xeon_gold/6136"
Facts about "Xeon Gold 6136 - Intel"
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Xeon Gold 6136 - Intel +, Xeon Gold 6136 - Intel +, Xeon Gold 6136 - Intel +, Xeon Gold 6136 - Intel + and Xeon Gold 6136 - Intel#io +
base frequency3,000 MHz (3 GHz, 3,000,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typeDMI 3.0 +
chipsetLewisburg +
clock multiplier30 +
core count12 +
core family6 +
core nameSkylake SP +
core steppingH0 +
cpuid0x50654 +
designerIntel +
familyXeon Gold +
first announcedApril 25, 2017 +
first launchedJuly 11, 2017 +
full page nameintel/xeon gold/6136 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Encryption Standard Instruction Set Extension +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Enhanced SpeedStep Technology +, Extended Page Tables +, Hyper-Threading Technology +, Intel VT-d +, Intel VT-x +, Intel vPro Technology +, Speed Shift Technology +, Transactional Synchronization Extensions +, Trusted Execution Technology + and Turbo Boost Technology 2.0 +
has intel enhanced speedstep technologytrue +
has intel speed shift technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size768 KiB (786,432 B, 0.75 MiB) +
l1d$ description8-way set associative +
l1d$ size384 KiB (393,216 B, 0.375 MiB) +
l1i$ description8-way set associative +
l1i$ size384 KiB (393,216 B, 0.375 MiB) +
l2$ description16-way set associative +
l2$ size12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) +
l3$ description11-way set associative +
l3$ size24.75 MiB (25,344 KiB, 25,952,256 B, 0.0242 GiB) +
ldateJuly 11, 2017 +
main imageFile:skylake sp (basic).png +
manufacturerIntel +
market segmentServer +
max case temperature358.15 K (85 °C, 185 °F, 644.67 °R) +
max cpu count4 +
max dts temperature103 °C +
max memory786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) +
max memory bandwidth119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels6 +
max pcie lanes48 +
microarchitectureSkylake (server) +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min dts temperature0 °C +
model number6136 +
nameXeon Gold 6136 +
packageFCLGA-3647 +
part numberCD8067303405800 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 2,460.00 (€ 2,214.00, £ 1,992.60, ¥ 254,191.80) +
s-specSR3B2 +
s-spec (qs)QMRX +
series6100 +
smp interconnectUPI +
smp interconnect links3 +
smp interconnect rate10.4 GT/s +
smp max ways4 +
socketLGA-3647 + and Socket P +
supported memory typeDDR4-2666 +
tdp150 W (150,000 mW, 0.201 hp, 0.15 kW) +
technologyCMOS +
thread count24 +
turbo frequency (1 core)3,700 MHz (3.7 GHz, 3,700,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +