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Difference between revisions of "intel/xeon gold/6130"
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{{intel title|Xeon Gold 6130}} | {{intel title|Xeon Gold 6130}} | ||
{{mpu | {{mpu | ||
| − | | future | + | |future=Yes |
| − | | name | + | |name=Xeon Gold 6130 |
| − | | no image | + | |no image=Yes |
| − | + | |designer=Intel | |
| − | + | |manufacturer=Intel | |
| − | + | |model number=6130 | |
| − | | designer | + | |part number=CD8067303409000 |
| − | | manufacturer | + | |s-spec=SR3B9 |
| − | | model number | + | |market=Server |
| − | | part number | + | |first announced=April 25, 2017 |
| − | + | |family=Xeon Gold | |
| − | + | |series=6100 | |
| − | | s-spec | + | |locked=Yes |
| − | + | |frequency=2,100 MHz | |
| − | | market | + | |turbo frequency1=3,700 MHz |
| − | | first announced | + | |bus type=DMI 3.0 |
| − | + | |bus links=4 | |
| − | + | |bus rate=8 GT/s | |
| − | + | |clock multiplier=21 | |
| − | + | |isa=x86-64 | |
| − | + | |isa family=x86 | |
| − | | family | + | |microarch=Skylake |
| − | | series | + | |platform=Purley |
| − | | locked | + | |chipset=Lewisburg |
| − | | frequency | + | |core name=Skylake SP |
| − | + | |core family=6 | |
| − | | turbo frequency1 | + | |core stepping=H0 |
| − | + | |process=14 nm | |
| − | + | |technology=CMOS | |
| − | + | |die area=<!-- XX mm² --> | |
| − | + | |word size=64 bit | |
| − | + | |core count=16 | |
| − | + | |thread count=32 | |
| − | + | |max cpus=2 | |
| − | | bus type | + | |v core tolerance=<!-- OR ... --> |
| − | | bus | + | |v io 2=<!-- OR ... --> |
| − | | bus rate | + | |tdp=125 W |
| − | + | |temp min=<!-- use TJ/TC whenever possible instead --> | |
| − | | clock multiplier | + | |tjunc min=<!-- .. °C --> |
| − | + | |package module 2=<!-------- USE ONLY IF MUST, OTHERWISE TRY TO USE MODULE ABOVE --------------> | |
| − | + | |turbo frequency=Yes | |
| − | + | |packaging=Yes | |
| − | | isa | + | |package 0=FCLGA-3647 |
| − | | isa | + | |package 0 type=LGA |
| − | | microarch | + | |package 0 pins=3647 |
| − | | platform | + | |socket 0=LGA-3647 |
| − | | chipset | + | |socket 0 type=LGA |
| − | | core name | ||
| − | | core family | ||
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| − | | core stepping | ||
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| − | | package module 2 | ||
| − | <!-------- USE ONLY IF MUST, OTHERWISE TRY TO USE MODULE ABOVE --------------> | ||
| − | | packaging | ||
| − | | package 0 | ||
| − | | package 0 type | ||
| − | | package 0 pins | ||
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}} | }} | ||
'''Xeon Gold 6130''' is a {{arch|64}} [[x86]] high-performance server [[hexadeca-core]] [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 6130 operates at 2.1 GHz with a TDP of 125 W and a {{intel|Turbo Boost|turbo frequency}} of 3.7 GHz for a single core. | '''Xeon Gold 6130''' is a {{arch|64}} [[x86]] high-performance server [[hexadeca-core]] [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 6130 operates at 2.1 GHz with a TDP of 125 W and a {{intel|Turbo Boost|turbo frequency}} of 3.7 GHz for a single core. | ||
Revision as of 00:57, 30 June 2017
Template:mpu Xeon Gold 6130 is a 64-bit x86 high-performance server hexadeca-core multiprocessor set to be introduced by Intel in the second quarter of 2017. This processor is based on the server configuration of the Skylake microarchitecture (a Skylake SP core) and is manufactured on Intel's 14 nm process. The 6130 operates at 2.1 GHz with a TDP of 125 W and a turbo frequency of 3.7 GHz for a single core.
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Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release. |
Cache
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Features
[Edit/Modify Supported Features]
Facts about "Xeon Gold 6130 - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Gold 6130 - Intel +, Xeon Gold 6130 - Intel +, Xeon Gold 6130 - Intel +, Xeon Gold 6130 - Intel +, Xeon Gold 6130 - Intel +, Xeon Gold 6130 - Intel +, Xeon Gold 6130 - Intel +, Xeon Gold 6130 - Intel +, Xeon Gold 6130 - Intel +, Xeon Gold 6130 - Intel +, Xeon Gold 6130 - Intel +, Xeon Gold 6130 - Intel + and Xeon Gold 6130 - Intel#io + |
| base frequency | 2,100 MHz (2.1 GHz, 2,100,000 kHz) + |
| bus links | 4 + |
| bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
| bus type | DMI 3.0 + |
| chipset | Lewisburg + |
| clock multiplier | 21 + |
| core count | 16 + |
| core family | 6 + |
| core name | Skylake SP + |
| core stepping | H0 + |
| cpuid | 0x50654 + |
| designer | Intel + |
| family | Xeon Gold + |
| first announced | April 25, 2017 + |
| first launched | July 11, 2017 + |
| full page name | intel/xeon gold/6130 + |
| has advanced vector extensions | true + |
| has advanced vector extensions 2 | true + |
| has advanced vector extensions 512 | true + |
| has ecc memory support | true + |
| has extended page tables support | true + |
| has feature | Advanced Encryption Standard Instruction Set Extension +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Enhanced SpeedStep Technology +, Extended Page Tables +, Hyper-Threading Technology +, Intel VT-d +, Intel VT-x +, Intel vPro Technology +, Speed Shift Technology +, Transactional Synchronization Extensions +, Trusted Execution Technology + and Turbo Boost Technology 2.0 + |
| has intel enhanced speedstep technology | true + |
| has intel speed shift technology | true + |
| has intel trusted execution technology | true + |
| has intel turbo boost technology 2 0 | true + |
| has intel vpro technology | true + |
| has intel vt-d technology | true + |
| has intel vt-x technology | true + |
| has locked clock multiplier | true + |
| has second level address translation support | true + |
| has simultaneous multithreading | true + |
| has transactional synchronization extensions | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| instance of | microprocessor + |
| isa | x86-64 + |
| isa family | x86 + |
| l1$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 512 KiB (524,288 B, 0.5 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 512 KiB (524,288 B, 0.5 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) + |
| l3$ description | 11-way set associative + |
| l3$ size | 22 MiB (22,528 KiB, 23,068,672 B, 0.0215 GiB) + |
| ldate | July 11, 2017 + |
| main image | .png) + |
| manufacturer | Intel + |
| market segment | Server + |
| max case temperature | 360.15 K (87 °C, 188.6 °F, 648.27 °R) + |
| max cpu count | 4 + |
| max dts temperature | 96 °C + |
| max memory | 786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) + |
| max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + |
| max memory channels | 6 + |
| max pcie lanes | 48 + |
| microarchitecture | Skylake (server) + |
| min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
| min dts temperature | 0 °C + |
| model number | 6130 + |
| name | Xeon Gold 6130 + |
| package | FCLGA-3647 + |
| part number | BX806736130 + and CD8067303409000 + |
| platform | Purley + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |
| release price | $ 1,894.00 (€ 1,704.60, £ 1,534.14, ¥ 195,707.02) + |
| s-spec | SR3B9 + |
| s-spec (qs) | QMS6 + |
| series | 6100 + |
| smp interconnect | UPI + |
| smp interconnect links | 3 + |
| smp interconnect rate | 10.4 GT/s + |
| smp max ways | 4 + |
| socket | LGA-3647 + and Socket P + |
| supported memory type | DDR4-2666 + |
| tdp | 125 W (125,000 mW, 0.168 hp, 0.125 kW) + |
| technology | CMOS + |
| thread count | 32 + |
| turbo frequency (1 core) | 3,700 MHz (3.7 GHz, 3,700,000 kHz) + |
| word size | 64 bit (8 octets, 16 nibbles) + |
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