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{{intel title|Xeon Gold 6128}}
 
{{intel title|Xeon Gold 6128}}
−
{{chip
+
{{mpu
−
|name=Xeon Gold 6128
+
| future              = Yes
−
|image=skylake sp (basic).png
+
| name               = Xeon Gold 6128
−
|designer=Intel
+
| no image            = Yes
−
|manufacturer=Intel
+
| image               =
−
|model number=6128
+
| image size          =
−
|part number=BX806736128
+
| caption            =  
−
|part number 2=CD8067303592600
+
| designer           = Intel
−
|s-spec=SR3J4
+
| manufacturer       = Intel
−
|s-spec qs=QN34
+
| model number       = 6128
−
|market=Server
+
| part number         = CD8067303592600
−
|first announced=April 25, 2017
+
| part number 1      =  
−
|first launched=July 11, 2017
+
| part number 2       =  
−
|release price=$1697.00
+
| s-spec             = SR3J4
−
|family=Xeon Gold
+
| s-spec 2            =  
−
|series=6100
+
| market             = Server
−
|locked=Yes
+
| first announced     = April 25, 2017
−
|frequency=3,400 MHz
+
| first launched     =
−
|turbo frequency1=3,700 MHz
+
| last order          =
−
|bus type=DMI 3.0
+
| last shipment      =  
−
|bus links=4
+
| release price       =  
−
|bus rate=8 GT/s
+
 
−
|clock multiplier=34
+
| family             = Xeon Gold
−
|cpuid=0x50654
+
| series             = 6100
−
|isa=x86-64
+
| locked             = Yes
−
|isa family=x86
+
| frequency           = 3.4 GHz
−
|microarch=Skylake (server)
+
| turbo frequency    =
−
|platform=Purley
+
| turbo frequency1   =
−
|chipset=Lewisburg
+
| turbo frequency2    =
−
|core name=Skylake SP
+
| turbo frequency3    =
−
|core family=6
+
| turbo frequency4    =
−
|core stepping=H0
+
| turbo frequency5    =
−
|process=14 nm
+
| turbo frequency6    =
−
|technology=CMOS
+
| turbo frequency7    =
−
|word size=64 bit
+
| turbo frequency8    =  
−
|core count=6
+
| bus type           = DMI 3.0
−
|thread count=12
+
| bus speed          =  
−
|max memory=768 GiB
+
| bus rate           = 8 GT/s
−
|max cpus=4
+
| bus links          = 4
−
|smp interconnect=UPI
+
| clock multiplier   = 34
−
|smp interconnect links=3
+
| cpuid               =
−
|smp interconnect rate=10.4 GT/s
+
| cpuid 2            =  
−
|tdp=115 W
+
 
−
|tcase min=0 °C
+
| isa family          = x86-64
−
|tcase max=74 °C
+
| isa                 = x86
−
|dts min=0 °C
+
| microarch           = Skylake
−
|dts max=100 °C
+
| platform           = Purley
−
|package name 1=intel,fclga_3647
+
| chipset             = Lewisburg
−
}}
+
| core name           = Skylake SP
−
'''Xeon Gold 6128''' is a {{arch|64}} [[hexa-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6128, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 3.4 GHz with a TDP of 115 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
+
| core family         =
 +
| core model          =  
 +
| core stepping       = H0
 +
| process             = 14 nm
 +
| transistors        =
 +
| technology         = CMOS
 +
| die area            = <!-- XX mm² -->
 +
| die width          =
 +
| die length          =
 +
| word size           = 64 bit
 +
| core count         =  
 +
| thread count       =  
 +
| max cpus            = 4
 +
| max memory          =  
 +
 
 +
| electrical          =  
 +
| power              =  
 +
| average power      =  
 +
| idle power          =  
 +
| v core              =  
 +
| v core tolerance    = <!-- OR ... -->
 +
| v core min         =  
 +
| v core max         =  
 +
| v io                =  
 +
| v io tolerance      =
 +
| v io 2              = <!-- OR ... -->
 +
| v io 3              =
 +
| sdp                =
 +
| tdp                =  
 +
| tdp typical        =
 +
| ctdp down          =
 +
| ctdp down frequency =
 +
| ctdp up             =
 +
| ctdp up frequency  =
 +
| temp min            = <!-- use TJ/TC whenever possible instead -->
 +
| temp max            =
 +
| tjunc min          = <!-- .. °C -->
 +
| tjunc max          =
 +
| tcase min          =
 +
| tcase max          =
 +
| tstorage min        =
 +
| tstorage max        =
 +
| tambient min        =
 +
| tambient max        =
  
−
== Cache ==
+
| package module 1    =  
−
{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
+
| package module 2    =  
−
The Xeon Gold 6128 features a considerably larger non-default 19.25 MiB of [[L3]], a size that would normally be found on a 14-core part.
+
<!-------- USE ONLY IF MUST, OTHERWISE TRY TO USE MODULE ABOVE -------------->
−
{{cache size
+
| packaging          = Yes
−
|l1 cache=384 KiB
+
| package 0          = FCLGA-3647
−
|l1i cache=192 KiB
+
| package 0 type      = LGA
−
|l1i break=6x32 KiB
+
| package 0 pins      = 3647
−
|l1i desc=8-way set associative
+
| package 0 pitch    =  
−
|l1d cache=192 KiB
+
| package 0 width    =  
−
|l1d break=6x32 KiB
+
| package 0 length    =  
−
|l1d desc=8-way set associative
+
| package 0 height    =  
−
|l1d policy=write-back
+
| socket 0            = LGA-3647
−
|l2 cache=6 MiB
+
| socket 0 type      = LGA
−
|l2 break=6x1 MiB
 
−
|l2 desc=16-way set associative
 
−
|l2 policy=write-back
 
−
|l3 cache=19.25 MiB
 
−
|l3 break=14x1.375 MiB
 
−
|l3 desc=11-way set associative
 
−
|l3 policy=write-back
 
 
}}
 
}}
 +
'''Xeon Gold 6128''' is a {{arch|64}} [[x86]] high-performance server [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 6128 operates at 3.4 GHz
  
−
== Memory controller ==
 
−
{{memory controller
 
−
|type=DDR4-2666
 
−
|ecc=Yes
 
−
|max mem=768 GiB
 
−
|controllers=2
 
−
|channels=6
 
−
|max bandwidth=119.21 GiB/s
 
−
|bandwidth schan=19.87 GiB/s
 
−
|bandwidth dchan=39.74 GiB/s
 
−
|bandwidth qchan=79.47 GiB/s
 
−
|bandwidth hchan=119.21 GiB/s
 
−
}}
 
  
−
== Expansions ==
+
{{unknown features}}
−
{{expansions
 
−
| pcie revision      = 3.0
 
−
| pcie lanes        = 48
 
−
| pcie config        = x16
 
−
| pcie config 2      = x8
 
−
| pcie config 3      = x4
 
−
}}
 
  
 
== Features ==  
 
== Features ==  
Line 117: Line 134:
 
|avx=Yes
 
|avx=Yes
 
|avx2=Yes
 
|avx2=Yes
−
|avx512f=Yes
+
|avx512=Yes
−
|avx512cd=Yes
 
−
|avx512er=No
 
−
|avx512pf=No
 
−
|avx512bw=Yes
 
−
|avx512dq=Yes
 
−
|avx512vl=Yes
 
−
|avx512ifma=No
 
−
|avx512vbmi=No
 
−
|avx5124fmaps=No
 
−
|avx5124vnniw=No
 
−
|avx512vpopcntdq=No
 
 
|abm=Yes
 
|abm=Yes
 
|tbm=No
 
|tbm=No
Line 143: Line 149:
 
|f16c=Yes
 
|f16c=Yes
 
|tbt1=No
 
|tbt1=No
−
|tbt2=Yes
+
|tbt2=No
 
|tbmt3=No
 
|tbmt3=No
 
|bpt=No
 
|bpt=No
 
|eist=Yes
 
|eist=Yes
−
|sst=Yes
+
|sst=No
 
|flex=No
 
|flex=No
 
|fastmem=No
 
|fastmem=No
−
|ivmd=Yes
 
−
|intelnodecontroller=Yes
 
−
|intelnode=Yes
 
−
|kpt=Yes
 
−
|ptt=Yes
 
−
|intelrunsure=Yes
 
−
|mbe=Yes
 
 
|isrt=No
 
|isrt=No
 
|sba=No
 
|sba=No
Line 164: Line 163:
 
|ipt=No
 
|ipt=No
 
|tsx=Yes
 
|tsx=Yes
−
|txt=Yes
+
|txt=No
 
|ht=Yes
 
|ht=Yes
 
|vpro=Yes
 
|vpro=Yes
Line 170: Line 169:
 
|vtd=Yes
 
|vtd=Yes
 
|ept=Yes
 
|ept=Yes
−
|mpx=No
+
|mpx=Yes
 
|sgx=No
 
|sgx=No
 
|securekey=No
 
|securekey=No
−
|osguard=No
+
|osguard=Yes
 
|3dnow=No
 
|3dnow=No
 
|e3dnow=No
 
|e3dnow=No
Line 180: Line 179:
 
|amdvi=No
 
|amdvi=No
 
|amdv=No
 
|amdv=No
−
|amdsme=No
 
−
|amdtsme=No
 
−
|amdsev=No
 
 
|rvi=No
 
|rvi=No
 
|smt=No
 
|smt=No
Line 188: Line 184:
 
|xfr=No
 
|xfr=No
 
}}
 
}}
−
 
−
== Frequencies ==
 
−
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 
−
{{frequency table
 
−
|freq_base=3,400 MHz
 
−
|freq_1=3,700 MHz
 
−
|freq_2=3,700 MHz
 
−
|freq_3=3,700 MHz
 
−
|freq_4=3,700 MHz
 
−
|freq_5=3,700 MHz
 
−
|freq_6=3,700 MHz
 
−
|freq_avx2_base=2,900 MHz
 
−
|freq_avx2_1=3,600 MHz
 
−
|freq_avx2_2=3,600 MHz
 
−
|freq_avx2_3=3,600 MHz
 
−
|freq_avx2_4=3,600 MHz
 
−
|freq_avx2_5=3,600 MHz
 
−
|freq_avx2_6=3,600 MHz
 
−
|freq_avx512_base=2,300 MHz
 
−
|freq_avx512_1=3,500 MHz
 
−
|freq_avx512_2=3,500 MHz
 
−
|freq_avx512_3=3,300 MHz
 
−
|freq_avx512_4=3,300 MHz
 
−
|freq_avx512_5=2,900 MHz
 
−
|freq_avx512_6=2,900 MHz
 
−
}}
 
−
 
−
== Benchmarks ==
 
−
{{benchmarks main
 
−
|
 
−
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00357.html|test_timestamp=2017-10-05 09:19:35-0400|chip_count=2|core_count=12|copies_count=24|vendor=HPE|system=ProLiant DL380 Gen10 (3.40 GHz, Intel Xeon Gold 6128)|SPECrate2017_fp_base=99.9|SPECrate2017_fp_peak=102}}
 
−
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00435.html|test_timestamp=2017-10-05 01:55:56-0400|chip_count=2|core_count=12|copies_count=24|vendor=HPE|system=ProLiant DL380 Gen10 (3.40 GHz, Intel Xeon Gold 6128)|SPECrate2017_int_base=82.7|SPECrate2017_int_peak=87.7}}
 
−
}}
 
−
 
−
[[Category:microprocessor models by intel based on skylake extreme core count die]]
 

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Retrieved from "https://en.wikichip.org/wiki/intel/xeon_gold/6128"
Facts about "Xeon Gold 6128 - Intel"
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"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon Gold 6128 - Intel +, Xeon Gold 6128 - Intel + and Xeon Gold 6128 - Intel#io +
base frequency3,400 MHz (3.4 GHz, 3,400,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typeDMI 3.0 +
chipsetLewisburg +
clock multiplier34 +
core count6 +
core family6 +
core nameSkylake SP +
core steppingH0 +
cpuid0x50654 +
designerIntel +
familyXeon Gold +
first announcedApril 25, 2017 +
first launchedJuly 11, 2017 +
full page nameintel/xeon gold/6128 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Transactional Synchronization Extensions +, Turbo Boost Technology 2.0 +, Speed Shift Technology +, Trusted Execution Technology +, Extended Page Tables + and Advanced Vector Extensions 512 +
has intel enhanced speedstep technologytrue +
has intel speed shift technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size384 KiB (393,216 B, 0.375 MiB) +
l1d$ description8-way set associative +
l1d$ size192 KiB (196,608 B, 0.188 MiB) +
l1i$ description8-way set associative +
l1i$ size192 KiB (196,608 B, 0.188 MiB) +
l2$ description16-way set associative +
l2$ size6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) +
l3$ description11-way set associative +
l3$ size19.25 MiB (19,712 KiB, 20,185,088 B, 0.0188 GiB) +
ldateJuly 11, 2017 +
main imageFile:skylake sp (basic).png +
manufacturerIntel +
market segmentServer +
max case temperature347.15 K (74 °C, 165.2 °F, 624.87 °R) +
max cpu count4 +
max dts temperature100 °C +
max memory786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) +
max memory bandwidth119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels6 +
max pcie lanes48 +
microarchitectureSkylake (server) +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min dts temperature0 °C +
model number6128 +
nameXeon Gold 6128 +
packageFCLGA-3647 +
part numberCD8067303592600 + and BX806736128 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 1,697.00 (€ 1,527.30, £ 1,374.57, ¥ 175,351.01) +
s-specSR3J4 +
s-spec (qs)QN34 +
series6100 +
smp interconnectUPI +
smp interconnect links3 +
smp interconnect rate10.4 GT/s +
smp max ways4 +
socketSocket P + and LGA-3647 +
supported memory typeDDR4-2666 +
tdp115 W (115,000 mW, 0.154 hp, 0.115 kW) +
technologyCMOS +
thread count12 +
turbo frequency (1 core)3,700 MHz (3.7 GHz, 3,700,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +