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| {{intel title|Xeon Gold 5120}} | | {{intel title|Xeon Gold 5120}} |
− | {{chip | + | {{mpu |
| |name=Xeon Gold 5120 | | |name=Xeon Gold 5120 |
| |image=skylake sp (basic).png | | |image=skylake sp (basic).png |
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| |part number 2=CD8067303535900 | | |part number 2=CD8067303535900 |
| |s-spec=SR3GD | | |s-spec=SR3GD |
− | |s-spec qs=QMXJ
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| |market=Server | | |market=Server |
| |first announced=July 11, 2017 | | |first announced=July 11, 2017 |
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| |release price=$1555.00 | | |release price=$1555.00 |
| |family=Xeon Gold | | |family=Xeon Gold |
− | |series=5100 | + | |series=5000 |
| |locked=Yes | | |locked=Yes |
| |frequency=2,200 MHz | | |frequency=2,200 MHz |
| |turbo frequency1=3,200 MHz | | |turbo frequency1=3,200 MHz |
| |clock multiplier=22 | | |clock multiplier=22 |
− | |cpuid=0x50654
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| |isa=x86-64 | | |isa=x86-64 |
| |isa family=x86 | | |isa family=x86 |
− | |microarch=Skylake (server) | + | |microarch=Skylake |
| |platform=Purley | | |platform=Purley |
| |chipset=Lewisburg | | |chipset=Lewisburg |
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| |core count=14 | | |core count=14 |
| |thread count=28 | | |thread count=28 |
| + | |max cpus=4 |
| |max memory=768 GiB | | |max memory=768 GiB |
− | |max cpus=4
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− | |smp interconnect=UPI
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− | |smp interconnect links=3
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− | |smp interconnect rate=10.4 GT/s
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| |tdp=105 W | | |tdp=105 W |
| |tcase min=0 °C | | |tcase min=0 °C |
| |tcase max=81 °C | | |tcase max=81 °C |
− | |dts min=0 °C
| + | |package module 1={{packages/intel/fclga-3647}} |
− | |dts max=92 °C
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− | |package name 1=intel,fclga_3647 | |
− | |successor=Xeon Gold 5220
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− | |successor link=intel/xeon_gold/5220
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| }} | | }} |
− | '''Xeon Gold 5120''' is a {{arch|64}} [[tetradeca-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 5120, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 1 {{x86|AVX-512}} [[FMA]] unit as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.2 GHz with a TDP of 105 W and a {{intel|turbo boost}} frequency of up to 3.2 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory. | + | '''Xeon Gold 5120''' is a {{arch|64}} [[tetradeca-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 5120, which is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 1 {{x86|AVX-512}} [[FMA]] unit as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.2 GHz with a TDP of 105 W and a {{intel|turbo boost}} frequency of up to 3.2 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory. |
| | | |
| == Cache == | | == Cache == |
− | {{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}} | + | {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} |
| {{cache size | | {{cache size |
| |l1 cache=896 KiB | | |l1 cache=896 KiB |
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| == Frequencies == | | == Frequencies == |
| {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} |
− | {{frequency table | + | {{frequency table}} |
− | |freq_base=2,200 MHz
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− | |freq_1=3,200 MHz
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− | |freq_2=3,200 MHz
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− | |freq_3=3,000 MHz
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− | |freq_4=3,000 MHz
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− | |freq_5=2,900 MHz
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− | |freq_6=2,900 MHz
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− | |freq_7=2,900 MHz
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− | |freq_8=2,900 MHz
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− | |freq_9=2,700 MHz
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− | |freq_10=2,700 MHz
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− | |freq_11=2,700 MHz
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− | |freq_12=2,700 MHz
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− | |freq_13=2,600 MHz
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− | |freq_14=2,600 MHz
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− | |freq_avx2_base=1,800 MHz
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− | |freq_avx2_1=3,100 MHz
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− | |freq_avx2_2=3,100 MHz
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− | |freq_avx2_3=2,900 MHz
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− | |freq_avx2_4=2,900 MHz
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− | |freq_avx2_5=2,700 MHz
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− | |freq_avx2_6=2,700 MHz
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− | |freq_avx2_7=2,700 MHz
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− | |freq_avx2_8=2,700 MHz
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− | |freq_avx2_9=2,300 MHz
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− | |freq_avx2_10=2,300 MHz
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− | |freq_avx2_11=2,300 MHz
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− | |freq_avx2_12=2,300 MHz
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− | |freq_avx2_13=2,200 MHz
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− | |freq_avx2_14=2,200 MHz
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− | |freq_avx512_base=1,200 MHz
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− | |freq_avx512_1=2,900 MHz
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− | |freq_avx512_2=2,900 MHz
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− | |freq_avx512_3=2,500 MHz
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− | |freq_avx512_4=2,500 MHz
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− | |freq_avx512_5=1,900 MHz
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− | |freq_avx512_6=1,900 MHz
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− | |freq_avx512_7=1,900 MHz
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− | |freq_avx512_8=1,900 MHz
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− | |freq_avx512_9=1,600 MHz
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− | |freq_avx512_10=1,600 MHz
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− | |freq_avx512_11=1,600 MHz
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− | |freq_avx512_12=1,600 MHz
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− | |freq_avx512_13=1,600 MHz
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− | |freq_avx512_14=1,600 MHz
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− | }} | |
− | | |
− | == Benchmarks ==
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− | {{benchmarks main
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− | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171003-00092.html|test_timestamp=2017-09-30 19:21:54-0400|chip_count=2|core_count=28|thread_count=28|vendor=Cisco Systems|system=Cisco UCS B200 M5 (Intel Xeon Gold 5120, 2.20GHz)|SPECspeed2017_fp_base=88.3|SPECspeed2017_fp_peak=89.3}}
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− | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171003-00101.html|test_timestamp=2017-09-30 13:35:47-0400|chip_count=2|core_count=28|thread_count=28|vendor=Cisco Systems|system=Cisco UCS B200 M5 (Intel Xeon Gold 5120, 2.20GHz)|SPECspeed2017_int_base=7.7|SPECspeed2017_int_peak=7.92}}
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− | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00339.html|test_timestamp=2017-10-18 08:00:36-0400|chip_count=2|core_count=28|copies_count=56|vendor=HPE|system=ProLiant DL380 Gen10 (2.20 GHz, Intel Xeon Gold 5120)|SPECrate2017_int_base=135|SPECrate2017_int_peak=143}}
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− | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00343.html|test_timestamp=2017-10-28 00:06:20-0400|chip_count=2|core_count=28|copies_count=56|vendor=HPE|system=ProLiant DL380 Gen10 (2.20 GHz, Intel Xeon Gold 5120)|SPECrate2017_fp_base=139|SPECrate2017_fp_peak=142}}
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− | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00404.html|test_timestamp=2017-10-26 01:03:26-0400|chip_count=2|core_count=28|copies_count=56|vendor=Cisco Systems|system=Cisco UCS B200 M5 (Intel Xeon Gold 5120, 2.20GHz)|SPECrate2017_fp_base=141|SPECrate2017_fp_peak=144}}
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− | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00413.html|test_timestamp=2017-10-26 20:27:13-0400|chip_count=2|core_count=28|copies_count=56|vendor=Cisco Systems|system=Cisco UCS B200 M5 (Intel Xeon Gold 5120, 2.20GHz)|SPECrate2017_int_base=136|SPECrate2017_int_peak=143}}
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− | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00416.html|test_timestamp=2017-10-27 07:02:34-0400|chip_count=2|core_count=28|thread_count=28|vendor=Cisco Systems|system=Cisco UCS B200 M5 (Intel Xeon Gold 5120, 2.20GHz)|SPECspeed2017_int_base=7.71|SPECspeed2017_int_peak=7.94}}
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− | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00418.html|test_timestamp=2017-10-27 12:48:28-0400|chip_count=2|core_count=28|thread_count=28|vendor=Cisco Systems|system=Cisco UCS B200 M5 (Intel Xeon Gold 5120, 2.20GHz)|SPECspeed2017_fp_base=88.4|SPECspeed2017_fp_peak=89.1}}
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− | }}
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− | [[Category:microprocessor models by intel based on skylake high core count die]]
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