Revision as of 01:29, 2 December 2016

Template:mpu Xeon E7-8837 is a 64-bit octa-core x86 data center microprocessor that supports up to 8 sockets. This first generation Xeon E7 processor, Westmere-based, operates at a base frequency of 2.66 GHz with turob frequency of 2.8 GHz for 2 active cores. This chip has a TDP of 130 W, supporting up to 4 channels of DDR3 with support of up to 4 TB of memory. This specific model does not have hyper-threading support.

Cache

Main article: Westmere § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 512 KiB 524,288 B 0.5 MiB L1I$ 256 KiB 262,144 B 0.25 MiB 8x32 KiB 4-way set associative write-back L1D$ 256 KiB 262,144 B 0.25 MiB 8x32 KiB 8-way set associative write-back L2$ 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB     8x256 KiB 8-way set associative write-back L3$ 24 MiB 24,576 KiB 25,165,824 B 0.0234 GiB     8x3 MiB 16-way set associative write-back

Graphics

This SoC has no integrated graphics processing unit.

Memory controller

Features

Template:mpu features