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Difference between revisions of "intel/xeon e3/e3-1505m v6"
< intel

(+cache)
(+memory controller)
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|l3 desc=16-way set associative
 
|l3 desc=16-way set associative
 
|l3 policy=write-back
 
|l3 policy=write-back
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR3L-1600
 +
|type 2=LPDDR3-2133
 +
|type 3=DDR4-2400
 +
|ecc=Yes
 +
|max mem=64 GiB
 +
|controllers=1
 +
|channels=2
 +
|max bandwidth=35.76 GiB/s
 +
|bandwidth schan=17.88 GiB/s
 +
|bandwidth dchan=35.76 GiB/s
 
}}
 
}}

Revision as of 21:19, 8 January 2017

Template:mpu Xeon E3-1505M v6 is a 64-bit quad-core entry-level workstations and dense servers x86 microprocessor introduced by Intel in 2017. This processor, which is based on the Kaby Lake microarchitecture, is manufactured on Intel's improved 14nm+ process. The E3-1505M v6 operates at 3 GHz with a TDP of 45 W and with a Turbo Boost frequency of 4 GHz for a single active core. This MPU supports up to 64 GiB of dual-channel ECC DDR4-2400 memory and incorporates Intel's HD Graphics P630 IGP operating at 350 MHz with a burst frequency of 1.1 GHz.

Cache

Main article: Kaby Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
L1I$128 KiB
0.125 MiB
131,072 B
1.220703e-4 GiB
4x32 KiB8-way set associativewrite-back
L1D$128 KiB
0.125 MiB
131,072 B
1.220703e-4 GiB
4x32 KiB8-way set associativewrite-back

L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  4x256 KiB4-way set associativewrite-back

L3$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  4x2 MiB16-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3L-1600, LPDDR3-2133, DDR4-2400
Supports ECCYes
Max Mem64 GiB
Controllers1
Channels2
Max Bandwidth35.76 GiB/s
62.222 GB/s
36,618.24 MiB/s
0.0349 TiB/s
0.0384 TB/s
Bandwidth
Single 17.88 GiB/s
Double 35.76 GiB/s
has ecc memory supporttrue +
l1$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
l1d$ description8-way set associative +
l1d$ size0.125 MiB (128 KiB, 131,072 B, 1.220703e-4 GiB) +
l1i$ description8-way set associative +
l1i$ size0.125 MiB (128 KiB, 131,072 B, 1.220703e-4 GiB) +
l2$ description4-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ description16-way set associative +
l3$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
max memory bandwidth35.76 GiB/s (62.222 GB/s, 36,618.24 MiB/s, 0.0349 TiB/s, 0.0384 TB/s) +
max memory channels2 +
supported memory typeDDR3L-1600 +, LPDDR3-2133 + and DDR4-2400 +