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{{intel title|Xeon D-2161I}}
 
{{intel title|Xeon D-2161I}}
 
{{chip
 
{{chip
 +
|future=Yes
 
|name=Xeon D-2161I
 
|name=Xeon D-2161I
−
|image=skylake-de (front).png
+
|no image=Yes
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
 
|model number=D-2161I
 
|model number=D-2161I
−
|part number=FH8067303534104
 
−
|s-spec=SR3ZN
 
 
|market=Server
 
|market=Server
 
|market 2=Embedded
 
|market 2=Embedded
−
|first announced=February 7, 2018
+
|release price=$962
−
|first launched=February 7, 2018
 
−
|release price=$962.00
 
 
|family=Xeon D
 
|family=Xeon D
 
|series=D-2000
 
|series=D-2000
 
|locked=Yes
 
|locked=Yes
 
|frequency=2,200 MHz
 
|frequency=2,200 MHz
−
|turbo frequency1=3,000 MHz
 
−
|bus type=DMI 3.0
 
−
|bus links=4
 
−
|bus rate=8 GT/s
 
−
|clock multiplier=22
 
 
|isa=x86-64
 
|isa=x86-64
 
|isa family=x86
 
|isa family=x86
 
|microarch=Skylake (server)
 
|microarch=Skylake (server)
−
|core name=Skylake DE
+
|core name=Skylake-D
−
|core stepping=M1
 
 
|process=14 nm
 
|process=14 nm
 
|technology=CMOS
 
|technology=CMOS
−
|mcp=Yes
 
−
|die count=2
 
 
|word size=64 bit
 
|word size=64 bit
 
|core count=12
 
|core count=12
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|max memory=512 GiB
 
|max memory=512 GiB
 
|tdp=90 W
 
|tdp=90 W
−
|package module 1={{packages/intel/fcbga-2518}}
 
 
}}
 
}}
−
'''Xeon D-2161I''' is a {{arch|64}} [[12-core]] high-performance [[x86]] server microprocessor introduced by [[Intel]] in early 2018 for the dense server and [[edge computing]] market segment. Fabricated on Intel's [[14 nm process]] based on the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture, this model operates at 2.2 GHz with a {{intel|Turbo Boost}} of up to 3.0 GHz and a [[TDP]] of 90 W. The D-2161I supports up to 512 GiB of quad-chanel DDR4-2133 ECC memory. This model is part of {{intel|Skylake DE|l=core}}'s [[part of::Edge Server and Cloud SKUs]].
+
'''Xeon D-2161I''' is a {{arch|64}} [[dodeca-core]] high-performance [[x86]] microserver processor set to be introduced by [[Intel]] in early [[2018]]. Fabricated on Intel's [[14 nm process|14nm+ process]] based on the {{intel|Skylake (server)|l=arch|Skylake microarchitecture}}, this chip operates at 2.2 GHz with a [[TDP]] of 90 W.
  
  
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|l3 desc=11-way set associative
 
|l3 desc=11-way set associative
 
|l3 policy=write-back
 
|l3 policy=write-back
−
}}
 
−
 
−
== Memory controller ==
 
−
{{memory controller
 
−
|type=DDR4-2133
 
−
|ecc=Yes
 
−
|max mem=512 GiB
 
−
|controllers=2
 
−
|channels=4
 
−
|max bandwidth=79.47 GiB/s
 
−
|bandwidth schan=15.89 GiB/s
 
−
|bandwidth dchan=31.78 GiB/s
 
−
|bandwidth qchan=63.57 GiB/s
 
−
|pae=46 bit
 
−
}}
 
−
 
−
== Expansions ==
 
−
This chip incorporates 20 high-speed I/O (HSIO) lanes that may be configured as up to 20 [[PCIe]] lanes, up to 14 SATA 3.0 ports, or up to 4 USB 3.0 ports.
 
−
{{expansions main
 
−
|
 
−
{{expansions entry
 
−
|type=PCIe
 
−
|pcie revision=3.0
 
−
|pcie lanes=32
 
−
|pcie config=x16
 
−
|pcie config 2=x8
 
−
|pcie config 3=x4
 
−
}}
 
−
{{expansions entry
 
−
|type=HSIO
 
−
|hsio lanes=20
 
−
}}
 
−
}}
 
−
== Networking ==
 
−
{{network
 
−
|eth opts=Yes
 
−
|10ge=Yes
 
−
|10ge ports=4
 
−
}}
 
−
== Features ==
 
−
{{x86 features
 
−
|real=Yes
 
−
|protected=Yes
 
−
|smm=Yes
 
−
|fpu=Yes
 
−
|x8616=Yes
 
−
|x8632=Yes
 
−
|x8664=Yes
 
−
|nx=Yes
 
−
|mmx=Yes
 
−
|emmx=Yes
 
−
|sse=Yes
 
−
|sse2=Yes
 
−
|sse3=Yes
 
−
|ssse3=Yes
 
−
|sse41=Yes
 
−
|sse42=Yes
 
−
|sse4a=No
 
−
|avx=Yes
 
−
|avx2=Yes
 
−
|avx512f=Yes
 
−
|avx512cd=Yes
 
−
|avx512er=No
 
−
|avx512pf=No
 
−
|avx512bw=Yes
 
−
|avx512dq=Yes
 
−
|avx512vl=Yes
 
−
|avx512ifma=No
 
−
|avx512vbmi=No
 
−
|avx5124fmaps=No
 
−
|avx5124vnniw=No
 
−
|avx512vpopcntdq=No
 
−
|avx512units=1
 
−
|abm=Yes
 
−
|tbm=No
 
−
|bmi1=Yes
 
−
|bmi2=Yes
 
−
|fma3=Yes
 
−
|fma4=No
 
−
|aes=Yes
 
−
|rdrand=Yes
 
−
|sha=No
 
−
|xop=No
 
−
|adx=Yes
 
−
|clmul=Yes
 
−
|f16c=Yes
 
−
|tbt1=No
 
−
|tbt2=Yes
 
−
|tbmt3=No
 
−
|bpt=No
 
−
|eist=Yes
 
−
|sst=Yes
 
−
|flex=No
 
−
|fastmem=No
 
−
|ivmd=Yes
 
−
|intelnodecontroller=No
 
−
|intelnode=No
 
−
|kpt=No
 
−
|ptt=No
 
−
|intelrunsure=No
 
−
|mbe=No
 
−
|isrt=No
 
−
|sba=No
 
−
|mwt=No
 
−
|sipp=No
 
−
|att=No
 
−
|ipt=Yes
 
−
|tsx=Yes
 
−
|txt=Yes
 
−
|ht=Yes
 
−
|vpro=Yes
 
−
|vtx=Yes
 
−
|vtd=Yes
 
−
|ept=Yes
 
−
|mpx=Yes
 
−
|sgx=No
 
−
|securekey=Yes
 
−
|osguard=Yes
 
−
|intqat=No
 
−
|3dnow=No
 
−
|e3dnow=No
 
−
|smartmp=No
 
−
|powernow=No
 
−
|amdvi=No
 
−
|amdv=No
 
−
|amdsme=No
 
−
|amdtsme=No
 
−
|amdsev=No
 
−
|rvi=No
 
−
|smt=No
 
−
|sensemi=No
 
−
|xfr=No
 
−
|mxfr=No
 
−
|amdpb=No
 
−
|amdpb2=No
 
−
}}
 
−
 
−
== Frequencies ==
 
−
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 
−
{{frequency table
 
−
|freq_base=2,200 MHz
 
−
|freq_1=3,000 MHz
 
−
|freq_2=3,000 MHz
 
−
|freq_3=2,800 MHz
 
−
|freq_4=2,800 MHz
 
−
|freq_5=2,800 MHz
 
−
|freq_6=2,800 MHz
 
−
|freq_7=2,800 MHz
 
−
|freq_8=2,800 MHz
 
−
|freq_9=2,800 MHz
 
−
|freq_10=2,800 MHz
 
−
|freq_11=2,800 MHz
 
−
|freq_12=2,800 MHz
 
−
|freq_avx2_1=2,900 MHz
 
−
|freq_avx2_2=2,900 MHz
 
−
|freq_avx2_3=2,700 MHz
 
−
|freq_avx2_4=2,700 MHz
 
−
|freq_avx2_5=2,700 MHz
 
−
|freq_avx2_6=2,700 MHz
 
−
|freq_avx2_7=2,700 MHz
 
−
|freq_avx2_8=2,700 MHz
 
−
|freq_avx2_9=2,700 MHz
 
−
|freq_avx2_10=2,700 MHz
 
−
|freq_avx2_11=2,700 MHz
 
−
|freq_avx2_12=2,700 MHz
 
−
|freq_avx512_1=2,800 MHz
 
−
|freq_avx512_2=2,800 MHz
 
−
|freq_avx512_3=2,600 MHz
 
−
|freq_avx512_4=2,600 MHz
 
−
|freq_avx512_5=2,500 MHz
 
−
|freq_avx512_6=2,500 MHz
 
−
|freq_avx512_7=2,500 MHz
 
−
|freq_avx512_8=2,500 MHz
 
−
|freq_avx512_9=2,200 MHz
 
−
|freq_avx512_10=2,200 MHz
 
−
|freq_avx512_11=2,200 MHz
 
−
|freq_avx512_12=2,200 MHz
 
 
}}
 
}}

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Retrieved from "https://en.wikichip.org/wiki/intel/xeon_d/d-2161i"
Facts about "Xeon D-2161I - Intel"
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Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon D-2161I - Intel#package + and Xeon D-2161I - Intel#pcie +
base frequency2,200 MHz (2.2 GHz, 2,200,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typeDMI 3.0 +
clock multiplier22 +
core count12 +
core nameSkylake DE +
core steppingM1 +
designerIntel +
die count2 +
familyXeon D +
first announcedFebruary 7, 2018 +
first launchedFebruary 7, 2018 +
full page nameintel/xeon d/d-2161i +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Encryption Standard Instruction Set Extension +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Enhanced SpeedStep Technology +, Extended Page Tables +, Hyper-Threading Technology +, Identity Protection Technology +, Intel VT-d +, Intel VT-x +, Intel vPro Technology +, Memory Protection Extensions +, OS Guard +, Secure Key Technology +, Speed Shift Technology +, Transactional Synchronization Extensions +, Trusted Execution Technology + and Turbo Boost Technology 2.0 +
has intel enhanced speedstep technologytrue +
has intel identity protection technology supporttrue +
has intel secure key technologytrue +
has intel speed shift technologytrue +
has intel supervisor mode execution protectiontrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
is multi-chip packagetrue +
isax86-64 +
isa familyx86 +
l1$ size768 KiB (786,432 B, 0.75 MiB) +
l1d$ description8-way set associative +
l1d$ size384 KiB (393,216 B, 0.375 MiB) +
l1i$ description8-way set associative +
l1i$ size384 KiB (393,216 B, 0.375 MiB) +
l2$ description16-way set associative +
l2$ size12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) +
l3$ description11-way set associative +
l3$ size16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) +
ldateFebruary 7, 2018 +
main imageFile:skylake-de (front).png +
manufacturerIntel +
market segmentEmbedded + and Server +
max cpu count1 +
max hsio lanes20 +
max memory524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) +
max memory bandwidth79.47 GiB/s (81,377.28 MiB/s, 85.33 GB/s, 85,330.263 MB/s, 0.0776 TiB/s, 0.0853 TB/s) +
max memory channels4 +
microarchitectureSkylake (server) +
model numberD-2161I +
nameXeon D-2161I +
number of avx-512 execution units1 +
packageFCBGA-2518 +
part numberFH8067303534104 +
part ofEdge Server and Cloud SKUs +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 962.00 (€ 865.80, £ 779.22, ¥ 99,403.46) +
s-specSR3ZN +
seriesD-2000 +
smp max ways1 +
supported memory typeDDR4-2133 +
tdp90 W (90,000 mW, 0.121 hp, 0.09 kW) +
technologyCMOS +
thread count24 +
turbo frequency (1 core)3,000 MHz (3 GHz, 3,000,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensionstrue +