Editing intel/xeon d

{{intel title|Xeon D}}
{{ic family
| title             = Intel Xeon D
| image             = broadwell de (front).png
| image size        = 250px
| caption           = Xeon D
| developer         = Intel
| manufacturer      = Intel
| type              = System in packages
| first announced   = March 9, 2015
| first launched    = March 9, 2015
| isa               = x86-64
| microarch         = Broadwell
| microarch 2       = Skylake (server)
| word              = 64 bit
| proc              = 14 nm
| tech              = CMOS
| clock min         = 1300 MHz
| clock max         = 2400 MHz
| package           = fcBGA-1667
| socket            = BGA-1667
}}
[[File:broadwell de (back).png|225px|right]]
'''Xeon D''' is a family of {{arch|64}} multi-core [[x86]] [[microserver]] single-chip processors introduced by [[Intel]] in March of 2015. Xeon D chips are aimed at filling the gap between the {{intel|Atom}} and the {{intel|Xeon E3}} families. Targeting the low-end server market, the Xeon D family puts priority on efficiency and networking - areas where dense, lower-power, lightweight [[hyperscale]] workloads are expected.

== History ==
The Xeon D began as a joint collaboration between [[Facebook]] and [[Intel]] in 2013. Yosemite is the codename for Facebook's open source modular chassis for the highly-concurrent but lower-power microservers. The design calls for dense nodes of lower power but highly concurrent workload which tends to be mostly memory-bandwidth-bound. While early designs where mostly based on the {{intel|Atom}} SoCs, their performance proved to be too much of a bottleneck on its own. Xeon D is a middle-tier family that's a step above {{intel|Atom}} in terms of performance, but below {{intel|Xeon E3}} power-wise. Xeon D is largely driven by high concurrency and better memory capabilities.

Currently, Intel offers two series of Xeon D parts - dense low-power and dense high-power parts.

{| class="wikitable"
|-
! Series !! Introduction !! Codename !! Microarchitecture
|-
! colspan="4" | Dense, Low-power
|-
| D-1500 || March, [[2015]] || {{intel|Broadwell DE|l=core}} || {{intel|Broadwell|l=arch}}
|-
| D-1600 || April, [[2019]] || {{intel|Hewitt Lake|l=core}} || {{intel|Broadwell|l=arch}}
|-
! colspan="4" | Dense, High-power
|-
| D-2100 || February, [[2018]] || {{intel|Skylake DE|l=core}} || {{intel|Skylake (server)|Skylake|l=arch}}
|}

== Dense Low-Power ==
=== D-1500 Series (Broadwell) ===
[[File:Intel-Xeon-processor-D-1500.png|right|300px]]
{{main|intel/microarchitectures/broadwell (server)|intel/cores/broadwell de|l1=Broadwell (Server) µarch|l2=Broadwell DE Core}}
First-generation of dense low-power Xeon D parts were introduced in early [[2015]] and are based on the {{intel|Broadwell (server)|Broadwell|l=arch}} microarchitecture. Fabricated on their [[14 nm process]], those parts incorporate up to [[16 cores|sixteen cores]] with a [[TDP]] of up to 65 W.

* '''TDP:''' 20-65 W
* '''Mem:''' 128 GiB dual-channel DDR4 ECC memory up to 2133/2400 MT/s. (128 GiB @ [[RDIMM]] 32 GiB/DIMM, 64 GiB @ UDIMM/SODIMM 16 GiB/DIMM)
* '''I/O:''' 32 PCIe 3/2 lanes (x24 Gen3 + x8 Gen2)
* '''ISA:''' Everything up to {{x86|AVX2}} ({{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}})
* '''Features:''' {{intel|SpeedStep}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Secure Key}}, and {{intel|OS Guard}}

All models are a single-chip solution, meaning both the [[CPU]] [[die]] and the [[chipset]] die are packaged together on the same substrate.
<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable tc4 tc5 tc11">
{{comp table header|main|11:List of Broadwell DE-based Processors}}
{{comp table header|cols|Launched|Price|C|T|TDP|L2|L3|%Frequency|%Turbo|QAT}}
{{comp table header|lsep|11:Edge Server and Cloud SKUs}}
{{#ask: [[Category:microprocessor models by intel]] [[core name::Broadwell DE]] [[model number ::!~*N]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?core count
 |?thread count
 |?tdp
 |?l2$ size
 |?l3$ size
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?has integrated intel quickassist technology
 |format=template
 |template=proc table 3
 |userparam=12:12
 |sort=model number
 |mainlabel=-
}}
{{comp table header|lsep|11:Network Edge and Storage SKUs}}
{{#ask: [[Category:microprocessor models by intel]] [[core name::Broadwell DE]] [[model number ::~*N]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?core count
 |?thread count
 |?tdp
 |?l2$ size
 |?l3$ size
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?has integrated intel quickassist technology
 |format=template
 |template=proc table 3
 |userparam=12:12
 |sort=model number
 |mainlabel=-
}}
{{comp table count|ask=[[Category:microprocessor models by intel]] [[core name::Broadwell DE]]}}
</table>
{{comp table end}}

=== D-1600 Series (Hewitt Lake) ===
{{main|intel/cores/hewitt lake|l1=Hewitt Lake core}}
Announced in February 2019, Hewitt Lake will be next-generation Xeon D processors.

== Dense High-Power ==
=== D-2100 Series (Skylake) ===
{{main|intel/microarchitectures/skylake (server)|intel/cores/skylake de|l1=Skylake (server) Microarchitecture|l2=Skylake DE core}}
Introduced in February [[2018]], Xeon D-2100 series processors are based on the {{intel|Skylake (server)|Skylake microarchitecture|l=arch}}. Those low-power variant range from [[4 cores|4]] to [[18 cores]] with {{intel|hyperthreading}} support. As with the previous generations, those chips are also a single-chip solution - the {{intel|Lewisburg|l=chipset}} [[chipset]] is incorporated into the same package as the processor. Being based on the new {{intel|Skylake (server)|Skylake microarchitecture|l=arch}} means those parts are also based on the mesh architecture which brought a much bigger L2 cache and supports twice as many memory channels. Additionally, all models also support {{x86|AVX-512}} with a single execution unit.

SKUs are suffixed with either I, T, and N or combination of multiple of those options:

* '''I''' - Integrated Ethernet
* '''T''' - High Temperature (90° [[tcase|T<sub>CASE</sub>]]) and extended reliability support
* '''N''' - Integrated Ethernet and Intel's {{intel|QuickAssist}} technology

All models have all the following features in common:

* '''Mem:''' Up 512 GiB of quad-channel DDR4 Memory
** DPC RDIMM and LRDIMM \w [[ECC]]
* '''I/O:''' 32 [[PCIe]] 3.0 Lanes + 20 configurable High-Speed I/O (HSIO) lanes
* '''TDP:''' < 110 W
* '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX512F, AVX512CD, AVX512BW, AVX512DQ, AVX512VL)
* '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}/{{intel|EPT}}, {{intel|VT-d}}, {{intel|TBT 2.0}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|SpeedStep}}, {{intel|Secure Key}}, {{intel|MPX}}, {{intel|OS Guard}}, and {{intel|RAS}}.

<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable tc4 tc5 tc12">
{{comp table header|main|11:List of Skylake DE-based Processors}}
{{comp table header|cols|Launched|Price|Cores|Threads|TDP|L2|L3|%Frequency|%Turbo|Memory|QAT}}
{{comp table header|lsep|11:Edge Server and Cloud SKUs}}
{{#ask: [[Category:microprocessor models by intel]] [[core name::Skylake DE]] [[part of::Edge Server and Cloud SKUs]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?core count
 |?thread count
 |?tdp
 |?l2$ size
 |?l3$ size
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?supported memory type
 |?has integrated intel quickassist technology
 |format=template
 |template=proc table 3
 |userparam=13:13
 |sort=model number
 |mainlabel=-
}}
{{comp table header|lsep|11:Network Edge and Storage SKUs}}
{{#ask: [[Category:microprocessor models by intel]] [[core name::Skylake DE]] [[part of::Network Edge and Storage SKUs]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?core count
 |?thread count
 |?tdp
 |?l2$ size
 |?l3$ size
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?supported memory type
 |?has integrated intel quickassist technology
 |format=template
 |template=proc table 3
 |userparam=13:13
 |sort=model number
 |mainlabel=-
}}
{{comp table header|lsep|11:Integrated QuickAssist Technology SKUs}}
{{#ask: [[Category:microprocessor models by intel]] [[core name::Skylake DE]] [[part of::Integrated QuickAssist Technology SKUs]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?core count
 |?thread count
 |?tdp
 |?l2$ size
 |?l3$ size
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?supported memory type
 |?has integrated intel quickassist technology
 |format=template
 |template=proc table 3
 |userparam=13:13
 |sort=model number
 |mainlabel=-
}}
{{comp table count|ask=[[Category:microprocessor models by intel]] [[core name::Skylake DE]]}}
</table>
{{comp table end}}

== See also ==
* Qualcomm {{qualcomm|Centriq}}
designer	Intel +
first announced	March 9, 2015 +
first launched	March 9, 2015 +
full page name	intel/xeon d +
instance of	integrated circuit family +
instruction set architecture	x86-64 +
main designer	Intel +
manufacturer	Intel +
microarchitecture	Broadwell + and Skylake (server) +
name	Intel Xeon D +
package	fcBGA-1667 +
process	14 nm (0.014 μm, 1.4e-5 mm) +
socket	BGA-1667 +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +