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* '''TDP:''' 20-65 W | * '''TDP:''' 20-65 W | ||
− | * '''Mem:''' 128 GiB dual-channel DDR4 ECC memory up to 2133/2400 MT/s. (128 GiB @ [[RDIMM]] 32 GiB/DIMM, 64 GiB @ UDIMM/SODIMM 16 GiB/DIMM | + | * '''Mem:''' 128 GiB dual-channel DDR4 ECC memory up to 2133/2400 MT/s. (128 GiB @ [[RDIMM]] 32 GiB/DIMM, 64 GiB @ UDIMM/SODIMM 16 GiB/DIMM |
* '''I/O:''' 32 PCIe 3/2 lanes (x24 Gen3 + x8 Gen2) | * '''I/O:''' 32 PCIe 3/2 lanes (x24 Gen3 + x8 Gen2) | ||
* '''ISA:''' Everything up to {{x86|AVX2}} ({{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}}) | * '''ISA:''' Everything up to {{x86|AVX2}} ({{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}}) |
Facts about "Xeon D - Intel"
designer | Intel + |
first announced | March 9, 2015 + |
first launched | March 9, 2015 + |
full page name | intel/xeon d + |
instance of | integrated circuit family + |
instruction set architecture | x86-64 + |
main designer | Intel + |
manufacturer | Intel + |
microarchitecture | Broadwell + and Skylake (server) + |
name | Intel Xeon D + |
package | fcBGA-1667 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
socket | BGA-1667 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |