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'''Xeon Bronze''' is a family of {{arch|64}} [[x86]] dual-socket multi-core entry-level server-class microprocessors introduced by [[Intel]] in 2017.
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'''Xeon Bronze''' is a family of {{arch|64}} [[x86]] dual-socket multi-core entry-level server microprocessors introduced by [[Intel]] in 2017.
  
 
== Overview ==
 
== Overview ==
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Released in July 2017, the Xeon Bronze are the successor to the {{intel|Xeon E5}}/{{intel|Xeon E7|E7}} families. Xeon Bronze is geared toward entry-level dual-socket server and workstation microprocessors. Those processors are ideally positioned for price-sensitive applications which require light-range workloads with enhanced security features and large memory. Additionally, those processors incorporate a number of {{intel|Ultra Path Interconnect}} (UPI) links. Unlike the higher tier Xeon families, the Xeon Bronze doesn't have {{intel|Turbo Boost Technology}} or {{intel|Hyper-Threading}} support.
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Released in July 2017, the Xeon Bronze are the successor to the {{intel|Xeon E5}}/{{intel|Xeon E7|E7}} families. Xeon Bronze is geared toward entry-level dual-socket server and workstation microprocessors.
  
 
== Members ==
 
== Members ==
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=== 3100-Series (Skylake) ===
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=== Skylake ===
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{{see also|intel/microarchitectures/skylake (server)|l1=Skylake µarch}}
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{{see also|intel/microarchitectures/skylake|l1=Skylake µarch}}
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First-generation Xeon Bronze processors were introduced in July 2017. Those chips were fabricated on a enhanced [[14 nm process|14nm+ process]] based on the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture which brought a {{intel|Skylake (Server)#Key changes from Broadwell|l=arch|relatively large}} SoC design change from the prior Xeon families. Those processors were the first to move to a {{intel|mesh interconnect}} which introduced a tile-based architecture, bringing the first implementation of {{x86|AVX-512}} along with a rearchitected cache hierarchy designed for server workloads. All of the bronze 3100-series microprocessors feature dual-socket capabilities with up to [[8 cores]] and 8 threads. Additionally, all Xeon Bronze processors support:
 
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* '''Proc:''' [[14 nm process]]
 
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* '''TDP:''' 85 W
 
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* '''Mem:''' 768 GiB hexa-channel DDR4-2133 ECC memory.
 
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* '''I/O:''' 48 PCIe Gen 3.0 lanes
 
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* '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, {{x86|AVX-512}}-{{x86|AVX512F|F}}/{{x86|AVX512CD|CD}}/{{x86|AVX512BW|BW}}/{{x86|AVX512DQ|DQ}}/{{x86|AVX512VL|VL}})
 
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* '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Volume Management Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT).
 
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All Xeon Bronze processors support QuickAssist Technology which is integrated on the chipset as well as the Omni-Path Architecture on the chipset as well as via discrete PCIe cards. All models also support 2 {{intel|Ultra Path Interconnect}} (UPI) links.
 
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{{comp table start}}
 
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<table class="comptable sortable tc4 tc5">
 
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{{comp table header|main|8:List of Skylake-based Xeon Bronze Processors}}
 
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{{comp table header 1|cols=Price, Launched, Cores, Threads, Frequency, TDP, L2$, L3$}}
 
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{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Bronze]] [[microarchitecture::Skylake (server)]]
 
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|?full page name
 
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|?model number
 
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|?release price
 
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|?first launched
 
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|?core count
 
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|?thread count
 
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|?base frequency#GHz
 
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|?tdp
 
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|?l2$ size
 
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|?l3$ size
 
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|format=template
 
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|template=proc table 3
 
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|userparam=10
 
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|mainlabel=-
 
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}}
 
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{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Bronze]] [[microarchitecture::Skylake (server)]]}}
 
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</table>
 
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{{comp table end}}
 
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=== 3200-Series (Cascade Lake) ===
 
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{{see also|intel/microarchitectures/cascade lake|l1=Cascade Lake µarch}}
 
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Second-generation Xeon Scalable Bronze was introduced in early 2019. Those processors are fabricated on an enhanced [[14 nm process]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture which allows for higher clock speeds and introduced a {{intel|Cascade Lake#Key changes from Skylake|l=arch|number of}} hardware changes against the various [[speculative execution]] [[side channel analysis|vulnerabilities]]. Those processors also introduced new {{x86|AVX-512 VNNI|new instructions}} for the [[acceleration]] of machine learning (inference) as well as support for [[persistent memory]]. All 3200-series Xeon Bronze processors support:
 
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* '''TDP:''' 85 W
 
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* '''Mem:''' 1 TiB hexa-channel DDR4-2133 ECC memory.
 
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* '''I/O:''' 48 PCIe 3 lanes
 
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* '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, {{x86|AVX-512}}-{{x86|AVX512F|F}}/{{x86|AVX512CD|CD}}/{{x86|AVX512BW|BW}}/{{x86|AVX512DQ|DQ}}/{{x86|AVX512VL|VL}}/{{x86|AVX512VNNI|VNNI}})
 
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* '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Volume Management Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT).
 
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All Xeon Bronze processors support QuickAssist Technology which is integrated on the chipset as well as the Omni-Path Architecture on the chipset as well as via discrete PCIe cards. All models also support 2 {{intel|Ultra Path Interconnect}} (UPI) links.
 
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<!-- NOTE:  
 
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           This table is generated automatically from the data in the actual articles.
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{{comp table start}}
 
{{comp table start}}
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<table class="comptable sortable tc4 tc5">
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<table class="comptable sortable tc13 tc14 tc15 tc16 tc17 tc18 tc19 tc20 tc21 tc22">
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{{comp table header|main|8:List of Cascade Lake-based Xeon Bronze Processors}}
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<tr class="comptable-header"><th>&nbsp;</th><th colspan="20">List of Skylake-based Xeon Bronze Processors</th></tr>
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{{comp table header 1|cols=Price, Launched, Cores, Threads, Frequency, TDP, L2$, L3$}}
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<tr class="comptable-header"><th>&nbsp;</th><th colspan="8">Main processor</th></tr>
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{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Bronze]] [[microarchitecture::Cascade Lake]]
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{{comp table header 1|cols=Price, Process, Launched, C, T, Freq, TDP, Max Mem}}
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{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Bronze]] [[microarchitecture::Skylake]]
 
  |?full page name
 
  |?full page name
 
  |?model number
 
  |?model number
 
  |?release price
 
  |?release price
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|?process
 
  |?first launched
 
  |?first launched
 
  |?core count
 
  |?core count
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  |?base frequency#GHz
 
  |?base frequency#GHz
 
  |?tdp
 
  |?tdp
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  |?l2$ size
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  |?max memory#GiB
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|?l3$ size
 
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|valuesep=,
 
 
  |format=template
 
  |format=template
 
  |template=proc table 3
 
  |template=proc table 3
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  |mainlabel=-
 
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}}
 
}}
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{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Bronze]] [[microarchitecture::Cascade Lake]]}}
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{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Bronze]] [[microarchitecture::Skylake]]}}
 
</table>
 
</table>
 
{{comp table end}}
 
{{comp table end}}

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Facts about "Xeon Bronze - Intel"
RDF feed
designerIntel +
first announcedMay 4, 2017 +
first launchedJuly 11, 2017 +
full page nameintel/xeon bronze +
instance ofmicroprocessor family +
instruction set architecturex86-64 +
main designerIntel +
manufacturerIntel +
microarchitectureSkylake +
nameXeon Bronze +
packageFCLGA-3647 +
process14 nm (0.014 μm, 1.4e-5 mm) +
socketLGA-3647 +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +