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From WikiChip
Tremont - Microarchitectures - Intel
< intel | microarchitectures
| Edit Values | |
| Tremont µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2018/2019 |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Instructions | |
| ISA | x86-64 |
| Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, SHA |
| Cores | |
| Core Names | Gemini Lake |
| Succession | |
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/tremont&oldid=76581"
Facts about "Tremont - Microarchitectures - Intel"
| codename | Tremont + |
| designer | Intel + |
| full page name | intel/microarchitectures/tremont + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Tremont + |
