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|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
| − | |introduction=2019 | + | |introduction=2018/2019 |
| − | |process=10 nm | + | |process=14/10 nm |
|type=Superscalar | |type=Superscalar | ||
|oooe=Yes | |oooe=Yes | ||
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|extension 11=PCLMUL | |extension 11=PCLMUL | ||
|extension 12=RDRND | |extension 12=RDRND | ||
| − | |extension 13 | + | |extension 13=SHA |
| − | + | |core name=Gemini Lake | |
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|predecessor=Goldmont Plus | |predecessor=Goldmont Plus | ||
|predecessor link=intel/microarchitectures/goldmont plus | |predecessor link=intel/microarchitectures/goldmont plus | ||
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}} | }} | ||
| − | '''Tremont''' is [[Intel]]'s successor to {{\\|Goldmont Plus}}, a [[10 nm]] microarchitecture for ultra-low power devices and microservers. | + | '''Tremont''' is [[Intel]]'s successor to {{\\|Goldmont Plus}}, a [[14 nm]] or [[10 nm]] microarchitecture for ultra-low power devices and microservers. |
== Codenames == | == Codenames == | ||
{| class="wikitable" | {| class="wikitable" | ||
| − | ! Platform !! Core Name | + | ! Platform !! Core Name |
|- | |- | ||
| − | + | | Jacobsville || {{intel|Elkhart Lake|l=core}}? | |
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| − | | Jacobsville || {{intel|Elkhart Lake|l=core}} | ||
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== Release Dates == | == Release Dates == | ||
| − | + | {{empty section}} | |
== Technology == | == Technology == | ||
| − | Tremont | + | Tremont appear to be planned for Intel's [[10 nm process]]. |
== Compiler support == | == Compiler support == | ||
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! Compiler !! Arch-Specific || Arch-Favorable | ! Compiler !! Arch-Specific || Arch-Favorable | ||
|- | |- | ||
| − | | [[ICC]] || <code>-march= | + | | [[ICC]] || <code>-march=?</code> || <code>-mtune=?</code> |
|- | |- | ||
| − | | [[GCC]] || <code>-march= | + | | [[GCC]] || <code>-march=?</code> || <code>-mtune=?</code> |
|- | |- | ||
| [[LLVM]] || <code>-march=tremont</code> || <code>-mtune=tremont</code> | | [[LLVM]] || <code>-march=tremont</code> || <code>-mtune=tremont</code> | ||
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== Architecture == | == Architecture == | ||
| − | + | {{future information}} | |
=== Key changes from {{\\|Goldmont Plus}} === | === Key changes from {{\\|Goldmont Plus}} === | ||
| − | * | + | * [[10 nm process]] (From [[14 nm]]) |
| − | + | {{expand list}} | |
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====New instructions ==== | ====New instructions ==== | ||
| − | + | Termont introduced a number of {{x86|extensions|new instructions}}: | |
* {{x86|CLWB|<code>CLWB</code>}} - Force cache line write-back without flush | * {{x86|CLWB|<code>CLWB</code>}} - Force cache line write-back without flush | ||
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* User wait instructions: TPAUSE, UMONITOR, UMWAIT | * User wait instructions: TPAUSE, UMONITOR, UMWAIT | ||
* Split Lock Detection - detection and cause an exception for split locks | * Split Lock Detection - detection and cause an exception for split locks | ||
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Facts about "Tremont - Microarchitectures - Intel"
| codename | Tremont + |
| designer | Intel + |
| first launched | 2019 + |
| full page name | intel/microarchitectures/tremont + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Tremont + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |
