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|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
− | |introduction=2019 | + | |introduction=2018/2019 |
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|type=Superscalar | |type=Superscalar | ||
|oooe=Yes | |oooe=Yes | ||
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|extension 11=PCLMUL | |extension 11=PCLMUL | ||
|extension 12=RDRND | |extension 12=RDRND | ||
− | |extension 13 | + | |extension 13=SHA |
− | + | |core name=Gemini Lake | |
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|predecessor=Goldmont Plus | |predecessor=Goldmont Plus | ||
|predecessor link=intel/microarchitectures/goldmont plus | |predecessor link=intel/microarchitectures/goldmont plus | ||
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}} | }} | ||
− | '''Tremont''' is | + | '''Tremont''' is a successor to {{\\|Goldmont Plus}}, [[Intel]]'s future microarchitecture for Intel's ultra-low power line of microprocessors. |
== Codenames == | == Codenames == | ||
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== Brands == | == Brands == | ||
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== Release Dates == | == Release Dates == | ||
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== Technology == | == Technology == | ||
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== Architecture == | == Architecture == | ||
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=== Key changes from {{\\|Goldmont Plus}} === | === Key changes from {{\\|Goldmont Plus}} === | ||
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====New instructions ==== | ====New instructions ==== | ||
− | + | Termont introduced a number of {{x86|extensions|new instructions}}: | |
* {{x86|CLWB|<code>CLWB</code>}} - Force cache line write-back without flush | * {{x86|CLWB|<code>CLWB</code>}} - Force cache line write-back without flush | ||
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* User wait instructions: TPAUSE, UMONITOR, UMWAIT | * User wait instructions: TPAUSE, UMONITOR, UMWAIT | ||
* Split Lock Detection - detection and cause an exception for split locks | * Split Lock Detection - detection and cause an exception for split locks | ||
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Facts about "Tremont - Microarchitectures - Intel"
codename | Tremont + |
designer | Intel + |
first launched | 2019 + |
full page name | intel/microarchitectures/tremont + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Tremont + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |