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* Performance | * Performance | ||
** [[IPC]] uplift ([[Intel]] self-reported average 18-20% IPC across proxy benchmarks such as [[SPEC CPU2006]]/[[SPEC CPU2017]]) | ** [[IPC]] uplift ([[Intel]] self-reported average 18-20% IPC across proxy benchmarks such as [[SPEC CPU2006]]/[[SPEC CPU2017]]) | ||
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* Front-end | * Front-end | ||
** 1.5x larger µOP cache (2.3K entries, up from 1536) | ** 1.5x larger µOP cache (2.3K entries, up from 1536) | ||
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** Improved [[branch predictor]] | ** Improved [[branch predictor]] | ||
** ITLB | ** ITLB | ||
− | *** | + | *** Double 2M page entries (16 entries, up from 8) |
** Larger IDQ (70 µOPs, up from 64) | ** Larger IDQ (70 µOPs, up from 64) | ||
** LSD can detect up to 70 µOP loops (up from 64) | ** LSD can detect up to 70 µOP loops (up from 64) | ||
* Back-end | * Back-end | ||
− | ** Wider allocation ( | + | ** Wider allocation (5-way, up from 4-way) |
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** 1.6x larger ROB (352, up from 224 entries) | ** 1.6x larger ROB (352, up from 224 entries) | ||
** Scheduler | ** Scheduler | ||
− | *** | + | *** Larger scheduler (160, up from 97 entries) |
*** Larger dispatch (10-way, up from 8-way) | *** Larger dispatch (10-way, up from 8-way) | ||
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* Execution Engine | * Execution Engine | ||
** Execution ports rebalanced | ** Execution ports rebalanced | ||
** 2x store data ports (up from 1) | ** 2x store data ports (up from 1) | ||
** 2x store address AGU (up from 1) | ** 2x store address AGU (up from 1) | ||
+ | ** New paired store capabilities | ||
+ | ** Replaced 2 generic AGUs with two load AGUs | ||
* Memory subsystem | * Memory subsystem | ||
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** LSU | ** LSU | ||
*** 1.8x more inflight loads (128, up from 72 entries) | *** 1.8x more inflight loads (128, up from 72 entries) | ||
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** 2x larger L2 cache (512 KiB, up from 256 KiB) | ** 2x larger L2 cache (512 KiB, up from 256 KiB) | ||
*** Larger STLBs | *** Larger STLBs | ||
− | **** | + | **** Larger 1G table (1024-entry, up from 16) |
+ | **** Larger 4k table (2048 entries, up from 1536) | ||
+ | **** New 1,024-entry 2M/4M table | ||
** 5-Level Paging | ** 5-Level Paging | ||
*** Large virtual address (57 bits, up from 48 bits) | *** Large virtual address (57 bits, up from 48 bits) | ||
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=== Block diagram === | === Block diagram === | ||
− | :[[File: | + | :[[File:sunny cove block diagram.svg|950px]] |
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== Overview == | == Overview == | ||
− | Sunny Cove is Intel's microarchitecture for | + | Sunny Cove is Intel's microarchitecture for the CPU core which is incorporated into a number of client and server chips that succeed {{\\|Palm Cove}} (and effectively the {{\\|Skylake (client)|Skylake}} series of derivatives). Sunny Cove is just the core which is implemented in a numerous chips made by Intel including {{\\|Lakefield}}, {{\\|Ice Lake (Client)}}, {{\\|Ice Lake (Server)}}, and the [[Nervana]] {{nervana|NNP}} accelerator. Sunny Cove introduces a large set of enhancements that significantly improves the performance of legacy code and new code through the extraction of parallelism as well as new features. Those include a significantly deep [[out-of-window]] pipeline, a wider execution back-end, higher load-store bandwidth, lower effective access latencies, and bigger caches. |
== Pipeline == | == Pipeline == |
Facts about "Sunny Cove - Microarchitectures - Intel"
codename | Sunny Cove + |
core count | 2 +, 4 +, 8 +, 10 +, 12 +, 16 +, 18 +, 20 +, 24 +, 26 +, 28 +, 32 +, 36 +, 38 + and 40 + |
designer | Intel + |
first launched | 2019 + |
full page name | intel/microarchitectures/sunny cove + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Sunny Cove + |
phase-out | 2021 + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |