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Latest revision | Your text | ||
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== Die == | == Die == | ||
=== Core === | === Core === | ||
− | * [[ | + | * [[10 nm process|10nm+ process]] |
− | * Core from an {{\\|Ice Lake (client)}} SoC | + | * Core from an {{\\|Ice Lake (client)|Ice Lake}} SoC |
* ~6.91 mm² die size | * ~6.91 mm² die size | ||
** ~3.5 mm x ~1.97 mm | ** ~3.5 mm x ~1.97 mm | ||
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:[[File:ice lake die core 2.png|500px]] | :[[File:ice lake die core 2.png|500px]] | ||
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=== Core group === | === Core group === | ||
− | * [[ | + | * [[10 nm process|10nm+ process]] |
* Quad-core from an {{\\|Ice Lake (client)|Ice Lake}} SoC | * Quad-core from an {{\\|Ice Lake (client)|Ice Lake}} SoC | ||
* ~30.73 mm² die size | * ~30.73 mm² die size |
Facts about "Sunny Cove - Microarchitectures - Intel"
codename | Sunny Cove + |
core count | 2 +, 4 +, 8 +, 10 +, 12 +, 16 +, 18 +, 20 +, 24 +, 26 +, 28 +, 32 +, 36 +, 38 + and 40 + |
designer | Intel + |
first launched | 2019 + |
full page name | intel/microarchitectures/sunny cove + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Sunny Cove + |
phase-out | 2021 + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |