From WikiChip
Editing intel/microarchitectures/spring hill
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 17: | Line 17: | ||
Spring Hill-based products are branded as the {{nervana|NNP-I}} 1000 series. | Spring Hill-based products are branded as the {{nervana|NNP-I}} 1000 series. | ||
− | |||
− | |||
− | |||
== Process technology == | == Process technology == | ||
Line 40: | Line 37: | ||
*** Tensilica Vision P6 DSP | *** Tensilica Vision P6 DSP | ||
** 3 MiB cache slice per pair | ** 3 MiB cache slice per pair | ||
− | |||
− | |||
=== Block Diagram === | === Block Diagram === | ||
Line 57: | Line 52: | ||
** 3 MiB | ** 3 MiB | ||
** 256 KiB/ICE (12 ICEs in total) | ** 256 KiB/ICE (12 ICEs in total) | ||
− | |||
* Deep SRAM | * Deep SRAM | ||
** 48 MiB | ** 48 MiB | ||
** 4 MiB/ICE (12 ICEs in total) | ** 4 MiB/ICE (12 ICEs in total) | ||
− | |||
* LLC | * LLC | ||
** 24 MiB | ** 24 MiB | ||
** 3 MiB/slice (8 slices in total) | ** 3 MiB/slice (8 slices in total) | ||
− | |||
* DRAM | * DRAM | ||
** 32 GiB | ** 32 GiB | ||
Line 72: | Line 64: | ||
== Overview == | == Overview == | ||
− | [[File:spring hill overview.svg|right| | + | [[File:spring hill overview.svg|right|450px]] |
Spring Hill is [[Intel]]'s first-generation SoC [[microarchitecture]] for [[neural processors]] designed for the acceleration of inference in the [[data center]]. The design targets data center inference workloads with a performance-power efficiency of close to 5 TOPS/W (4.8 in practice) in a power envelope of 10-50 W in order to main a light PCIe-driven [[accelerator card]] form factor such as [[M.2]]. The form factor and power envelope is selected for its ease of integration into existing infrastructure without additional cooling/power capacity. | Spring Hill is [[Intel]]'s first-generation SoC [[microarchitecture]] for [[neural processors]] designed for the acceleration of inference in the [[data center]]. The design targets data center inference workloads with a performance-power efficiency of close to 5 TOPS/W (4.8 in practice) in a power envelope of 10-50 W in order to main a light PCIe-driven [[accelerator card]] form factor such as [[M.2]]. The form factor and power envelope is selected for its ease of integration into existing infrastructure without additional cooling/power capacity. | ||
Line 108: | Line 100: | ||
:2 Applications, Batch size of 1: | :2 Applications, Batch size of 1: | ||
− | :[[File:sph batch 1x2.svg| | + | :[[File:sph batch 1x2.svg|300px]] |
</div> | </div> | ||
<div style="float: left;"> | <div style="float: left;"> | ||
Line 114: | Line 106: | ||
:6 Applications, Batch size of 4: | :6 Applications, Batch size of 4: | ||
− | :[[File:sph batch 4x6.svg| | + | :[[File:sph batch 4x6.svg|300px]] |
</div> | </div> | ||
</div> | </div> | ||
{{clear}} | {{clear}} | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
== Board == | == Board == | ||
[[File:spring hill board.JPG|right|thumb]] | [[File:spring hill board.JPG|right|thumb]] | ||
− | + | [[M.2]] board: | |
− | [[M.2]] board | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | + | :[[File:sph board.jpg|700px]] | |
− | |||
== Die == | == Die == |
Facts about "Spring Hill - Microarchitectures - Intel"
codename | Spring Hill + |
core count | 2 + |
designer | Intel + |
first launched | May 2019 + |
full page name | intel/microarchitectures/spring hill + |
instance of | microarchitecture + |
manufacturer | Intel + |
name | Spring Hill + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |
processing element count | 10 +, 12 + and 8 + |