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− | {{intel title|Spring Hill|arch}} | + | {{intel title|Spring Hill|l=arch}} |
{{microarchitecture | {{microarchitecture | ||
|atype=NPU | |atype=NPU | ||
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− | '''Spring Hill''' | + | '''Spring Hill''' is a [[10 nm]] microarchitecture designed by [[Intel]] for their [[inference]] [[neural processors]]. Spring Hill was developed by the Israel Haifa Development Center (IDC). |
Spring Hill-based products are branded as the {{nervana|NNP-I}} 1000 series. | Spring Hill-based products are branded as the {{nervana|NNP-I}} 1000 series. | ||
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== Process technology == | == Process technology == | ||
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== Architecture == | == Architecture == | ||
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=== Block Diagram === | === Block Diagram === | ||
==== SoC Overview ==== | ==== SoC Overview ==== | ||
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==== Sunny Cove Core ==== | ==== Sunny Cove Core ==== | ||
See {{intel|sunny cove#Block diagram|Sunny Cove § Block diagram|l=arch}}. | See {{intel|sunny cove#Block diagram|Sunny Cove § Block diagram|l=arch}}. | ||
− | ==== Inference | + | ==== Inference Engine (ICE) ==== |
− | + | {{empty section}} | |
=== Memory Organization === | === Memory Organization === | ||
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* LLC | * LLC | ||
** 24 MiB | ** 24 MiB | ||
** 3 MiB/slice (8 slices in total) | ** 3 MiB/slice (8 slices in total) | ||
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* DRAM | * DRAM | ||
− | ** | + | ** 64 GiB |
** 2x64b or 4x32b LPDDR4x-4200 | ** 2x64b or 4x32b LPDDR4x-4200 | ||
** 67.2 GB/s | ** 67.2 GB/s | ||
== Overview == | == Overview == | ||
− | [[File:spring hill overview.svg|right| | + | [[File:spring hill overview.svg|right|450px]] |
Spring Hill is [[Intel]]'s first-generation SoC [[microarchitecture]] for [[neural processors]] designed for the acceleration of inference in the [[data center]]. The design targets data center inference workloads with a performance-power efficiency of close to 5 TOPS/W (4.8 in practice) in a power envelope of 10-50 W in order to main a light PCIe-driven [[accelerator card]] form factor such as [[M.2]]. The form factor and power envelope is selected for its ease of integration into existing infrastructure without additional cooling/power capacity. | Spring Hill is [[Intel]]'s first-generation SoC [[microarchitecture]] for [[neural processors]] designed for the acceleration of inference in the [[data center]]. The design targets data center inference workloads with a performance-power efficiency of close to 5 TOPS/W (4.8 in practice) in a power envelope of 10-50 W in order to main a light PCIe-driven [[accelerator card]] form factor such as [[M.2]]. The form factor and power envelope is selected for its ease of integration into existing infrastructure without additional cooling/power capacity. | ||
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Spring Hill borrows a number of other components from {{intel|Ice Lake (client)|Ice Lake|l=arch}} including the [[FIVR]] and the power management controller which allows the ICEs and SNC to dynamically shift the power to the various execution units depending on the available thermal headroom and the total package power consumption. Various power-related scheduling is also done ahead of time by the compiler. Feeding Spring Hill is a also an [[LPDDR4x]] [[memory controller]] that supports either dual-channel 64-bit or quad-channel 32-bit (128b in total) with rates up to 4200 MT/s for a total memory bandwidth of 67.2 GB/s. | Spring Hill borrows a number of other components from {{intel|Ice Lake (client)|Ice Lake|l=arch}} including the [[FIVR]] and the power management controller which allows the ICEs and SNC to dynamically shift the power to the various execution units depending on the available thermal headroom and the total package power consumption. Various power-related scheduling is also done ahead of time by the compiler. Feeding Spring Hill is a also an [[LPDDR4x]] [[memory controller]] that supports either dual-channel 64-bit or quad-channel 32-bit (128b in total) with rates up to 4200 MT/s for a total memory bandwidth of 67.2 GB/s. | ||
− | == Inference | + | == Inference Engine (ICE) == |
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== Board == | == Board == | ||
[[File:spring hill board.JPG|right|thumb]] | [[File:spring hill board.JPG|right|thumb]] | ||
− | + | [[M.2]] board: | |
− | [[M.2]] board | ||
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− | + | :[[File:sph board.jpg|700px]] | |
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== Die == | == Die == |
Facts about "Spring Hill - Microarchitectures - Intel"
codename | Spring Hill + |
core count | 2 + |
designer | Intel + |
first launched | May 2019 + |
full page name | intel/microarchitectures/spring hill + |
instance of | microarchitecture + |
manufacturer | Intel + |
name | Spring Hill + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |
processing element count | 10 +, 12 + and 8 + |