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Spring Hill is [[Intel]]'s first-generation SoC [[microarchitecture]] for [[neural processors]] designed for the acceleration of inference in the [[data center]]. The design targets data center inference workloads with a performance-power efficiency of close to 5 TOPS/W (4.8 in practice) in a power envelope of 10-50 W in order to main a light PCIe-driven [[accelerator card]] form factor such as [[M.2]]. The form factor and power envelope is selected for its ease of integration into existing infrastructure without additional cooling/power capacity. | Spring Hill is [[Intel]]'s first-generation SoC [[microarchitecture]] for [[neural processors]] designed for the acceleration of inference in the [[data center]]. The design targets data center inference workloads with a performance-power efficiency of close to 5 TOPS/W (4.8 in practice) in a power envelope of 10-50 W in order to main a light PCIe-driven [[accelerator card]] form factor such as [[M.2]]. The form factor and power envelope is selected for its ease of integration into existing infrastructure without additional cooling/power capacity. | ||
− | Spring Hill borrows a lot from the client {{intel|Ice Lake (Client)|Ice Lake|l=arch}} SoC. To that end, Spring Hill features two full-fledge {{intel|Sunny Cove|l=arch}} [[big cores]]. The primary purpose of the [[big cores]] here is to execute the orchestration software and runtime logic determined by the compiler ahead of time. Additionally, since they come with {{x86|AVX-512}} along with the {{x86|AVX VNNI}} {{x86|extension}} for inference acceleration, they can be used to run any desired user-specified code, providing an additional layer of programmability. Instead of the traditional integrated graphics and additional cores, Intel integrated up to twelve custom inference compute engines attached to the {{intel|ring bus}} in pairs. The ICEs have been designed for inference workloads (see [[#Inference Compute Engine (ICE)|§ Inference Compute Engine (ICE)]]). The ICEs may each be running independent inference workloads or they may be combined to handle larger models faster. Attached to each pair of ICEs and the {{intel|Sunny Cove|SNC|l=arch}} cores are 3 MiB slices of [[last level cache]] for a total of 24 MiB of on-die shared LLC cache. While the LLC is hardware managed, there is some software provisions that can be used to hint the hardware in terms of expectations by dictating service levels and priorities. | + | Spring Hill borrows a lot from the client {{intel|Ice Lake (Client)|Ice Lake|l=arch}} SoC. To that end, Spring Hill features two full-fledge {{intel|Sunny Cove|l=arch}} [[big cores]]. The primary purpose of the [[big cores]] here is to execute the orchestration software and runtime logic determined by the compiler ahead of time. Additionally, since they come with {{x86|AVX-512}} along with the {{x86|AVX VNNI}} {{x86|extension}} for inference acceleration, they can be used to run any desired user-specified code, providing an additional layer of programmability. Instead of the traditional integrated graphics and additional cores, Intel integrated up to twelve custom inference and compute engines attached to the {{intel|ring bus}} in pairs. The ICEs have been designed for inference workloads (see [[#Inference and Compute Engine (ICE)|§ Inference and Compute Engine (ICE)]]). The ICEs may each be running independent inference workloads or they may be combined to handle larger models faster. Attached to each pair of ICEs and the {{intel|Sunny Cove|SNC|l=arch}} cores are 3 MiB slices of [[last level cache]] for a total of 24 MiB of on-die shared LLC cache. While the LLC is hardware managed, there is some software provisions that can be used to hint the hardware in terms of expectations by dictating service levels and priorities. |
In order to simplify the ICE-ICE, ICE-SNC, and even ICE-Host communication, Spring Hill incorporates a special synchronization unit that allows for efficient communication between the units. | In order to simplify the ICE-ICE, ICE-SNC, and even ICE-Host communication, Spring Hill incorporates a special synchronization unit that allows for efficient communication between the units. |
Facts about "Spring Hill - Microarchitectures - Intel"
codename | Spring Hill + |
core count | 2 + |
designer | Intel + |
first launched | May 2019 + |
full page name | intel/microarchitectures/spring hill + |
instance of | microarchitecture + |
manufacturer | Intel + |
name | Spring Hill + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |
processing element count | 10 +, 12 + and 8 + |